AnsweredAssumed Answered

vrf JTAG (again!)

Question asked by kirk_reed on Dec 12, 2004
Greg,

Not sure if I had replied to your original post about JTAG (was it the
one back in February?).

Currently I have utilized the JTAG (company's name is JTAG Technologies)
parr port 3705 (the hardware on the parr port driving the boundary scan
device).  My implementation is not fancy.  I just compiled little .pat
files from within their software "Active Test" and executed them through
a dos command from within Vee.  It only returns a pass or fail
indication, but I broke it into little steps so if one failed, I would
just report to the operator which pin failed and under what conditions.
I have developed two separate tests, with each one only having one
boundary scan device.  This just opened the possibilities to use
boundary scan, and I exploited it very quickly within vee.  My original
purpose was to get a tool to set pins on the device hi or lo, writing
and reading the device from the edge connectors of the board under test.
Jtag did what I wanted, so I bought it and it did exactly what I wanted.
The test can be faster if I execute more vectors at a time, but I still
have to setup stimulus and response from outside the board, so I am
limited there.

Next month I start a new board, and will use their tools to develop a
more complex test, so I will be learning more next month.  It might be
done totally with Jtag, and maybe not even Vee.

If you think this sounds like something you need, get in touch with me
and we can talk further.

Regards,

Kirk Reed
Agilent Technologies
Wilmington, DE
Kirk_reed@agilent.com
302-633-8559


-----Original Message-----
From: Gregg C Levine [mailto:landocalrissian@att.net]
Sent: Sunday, December 05, 2004 3:06 PM
To: VRF
Subject: [vrf] JTAG (again!)

Hello from Gregg C Levine
Where are we now regarding the JTAG concepts and VEE?

As it happens before posting this message I decided to try Shawn's
archive.
Nice, but only 17 on the subject? And some of them had my name on them.

Basically I am planning on adapting the Parallel Port DLL that was
discussed
here last week for that purpose. The hardware is one of adapting the
current
one from Xilinix or related companies for the job.

But I'm still searching for advice concerning how to construct VEE
programs
for this one.
----------
Gregg C Levine landocalrissian atsign att dot net
~~This Signature supports the Rebel Alliance to Restore The Republic~~
"They were in the wrong place at the wrong time, naturally they became
heroes."
Princess Leia Organa of Alderaan, Senator


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