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vrf HP 1662A Logic Analyzer problem

Question asked by VRFuser on Oct 22, 2003
Latest reply on Oct 22, 2003 by VRFuser
Hi VRF!!!
I have a question about HP 1662A Logic Analyzer.
I trying to develop a test program for a Digital circuit and observing the
output pins of a FPGA using Logic Analy.
After triggering the Logic analyzer, i am trying to download the data from
logic analyzer to my Vee program.

Before downloading the data first of all i mask the Module event status
enable register with 1 which informs me about the "measurement satisfactory"
condition. So after triggering the LA, i am checking the MESR register for
bit#1.
Here is my question although masking with 1, (I expect 0 or 1 i.e 0 for not
complete, 1 for measurement complete) i'm getting strange values (which are
never 1).
Although i can see the patterns generated on the screen, i am not getting
correct register value.
Is there any other way to understand whether a measurement is complete or am
i doing sth wrong in this method.

Any help will be greatly appreciated.
Best Regards.


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