Subject: Low-fidelity User Testing: RFIC Integrated Design Flow
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From: LOCKHART_SCOTT/HP-Sonoma_om1@boi164
TO: BAKER_GAIL/HP-Sonoma_unix1@boi164,
BISCHOF_STAN/HP-Sonoma_om2@boi164,
KESSLER_JULIE/HP-SanJose_om1@boi164,
YAP_HOW-SIANG/HP-Sonoma_om1@boi164,
ZHANG_CINDY/HP-Sonoma_om1@boi164
CC: ALPINE_JOHN/HP-Sonoma_om1@boi164,
ARANHA_MARIO/HP-Sonoma_om1@boi164,
HAYNES_TERRY/HP-Sonoma_om1@boi164,
LERNER_LARRY/HP-Sonoma_om1@boi164,
NYE_JANE/HP-Sonoma_om1@boi164,
PENNINGTON_MARGARET/HP-Sonoma_om3@boi164,
PETERSEN_MARC/HP-Sonoma_om1@boi164,
PHILLIPS_TOM/HP-Sonoma_om1@boi164
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Hi,
On Thursday, April 9, 1998, we will be conducting low-fidelity user
testing of HP EEsof's RFIC Integrated Design Flow tool. You are
invited to take part in this first round of low-fidelity user testing.
The RFIC Integrated Design Flow tool is a framework integration
product that will give RFIC designers the full capability of HP ADS
simulation tools yet enable them to maintain their designs in the
Cadence framework. The integration will be based on Inter-Process
Communication (IPC) as opposed to File Interchange (IFF). Normal user
familiarity with both Cadence and ADS will be needed. The initial
product offering will be a licensed module in ADS 1.5.
If you are able to take part in this first round of user testing,
please select a time slot and reply to this message at your earliest
convenience.
As usual, lunch is on us.
Thanks,
Scott
----------------------------------------------------------------------
RFIC Integrated Design Flow low-fidelity user testing
----------------------------------------------------------------------
Name:
Job:
Division:
Phone:
Thursday, April 9, 1998
( ) 8:30 am
( )10:30 am
( ) 1:00 pm
( ) 3:00 pm
Please respond by Friday, April 3, 1998
--openmail-part-0f3ba709-00000002--
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From: LOCKHART_SCOTT/HP-Sonoma_om1@boi164
TO: BAKER_GAIL/HP-Sonoma_unix1@boi164,
BISCHOF_STAN/HP-Sonoma_om2@boi164,
KESSLER_JULIE/HP-SanJose_om1@boi164,
YAP_HOW-SIANG/HP-Sonoma_om1@boi164,
ZHANG_CINDY/HP-Sonoma_om1@boi164
CC: ALPINE_JOHN/HP-Sonoma_om1@boi164,
ARANHA_MARIO/HP-Sonoma_om1@boi164,
HAYNES_TERRY/HP-Sonoma_om1@boi164,
LERNER_LARRY/HP-Sonoma_om1@boi164,
NYE_JANE/HP-Sonoma_om1@boi164,
PENNINGTON_MARGARET/HP-Sonoma_om3@boi164,
PETERSEN_MARC/HP-Sonoma_om1@boi164,
PHILLIPS_TOM/HP-Sonoma_om1@boi164
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Hi,
On Thursday, April 9, 1998, we will be conducting low-fidelity user
testing of HP EEsof's RFIC Integrated Design Flow tool. You are
invited to take part in this first round of low-fidelity user testing.
The RFIC Integrated Design Flow tool is a framework integration
product that will give RFIC designers the full capability of HP ADS
simulation tools yet enable them to maintain their designs in the
Cadence framework. The integration will be based on Inter-Process
Communication (IPC) as opposed to File Interchange (IFF). Normal user
familiarity with both Cadence and ADS will be needed. The initial
product offering will be a licensed module in ADS 1.5.
If you are able to take part in this first round of user testing,
please select a time slot and reply to this message at your earliest
convenience.
As usual, lunch is on us.
Thanks,
Scott
----------------------------------------------------------------------
RFIC Integrated Design Flow low-fidelity user testing
----------------------------------------------------------------------
Name:
Job:
Division:
Phone:
Thursday, April 9, 1998
( ) 8:30 am
( )10:30 am
( ) 1:00 pm
( ) 3:00 pm
Please respond by Friday, April 3, 1998
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