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Low-fidelity User Testing: RFIC Integrated Design Flow

Question asked by VRFuser on Mar 30, 1998
Subject: Low-fidelity User Testing: RFIC Integrated Design Flow
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     Hi,
    
     On Thursday, April 9, 1998, we will be conducting low-fidelity user
     testing of HP EEsof's RFIC Integrated Design Flow tool.  You are
     invited to take part in this first round of low-fidelity user testing.
    
     The RFIC Integrated Design Flow tool is a framework integration
     product that will give RFIC designers the full capability of HP ADS
     simulation tools yet enable them to maintain their designs in the
     Cadence framework.  The integration will be based on Inter-Process
     Communication (IPC) as opposed to File Interchange (IFF).  Normal user
     familiarity with both Cadence and ADS will be needed.  The initial
     product offering will be a licensed module in ADS 1.5.
    
     If you are able to take part in this first round of user testing,
     please select a time slot and reply to this message at your earliest
     convenience.
    
     As usual, lunch is on us.
    
     Thanks,
     Scott
    
     ----------------------------------------------------------------------
     RFIC Integrated Design Flow low-fidelity user testing
     ----------------------------------------------------------------------
     Name:
     Job:
     Division:
     Phone:
    
     Thursday, April 9, 1998
    
        ( ) 8:30 am
        ( )10:30 am
        ( ) 1:00 pm
        ( ) 3:00 pm
    
     Please respond by Friday, April 3, 1998

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