Originally posted Oct 30, 2014
An alternative to PLLs changes the phase noise landscape
Phase-locked loops (PLLs) in radio receivers date back to the first half of the 20th Century, and made their way into test equipment in the second half. In the 1970s, PLLs supplanted direct analog synthesizers in many signal generators and were used as the local oscillator (LO) sections of some spectrum analyzers.
In another example of Moore’s Law, the late 1970s and 1980s saw rapid improvements in PLL technology, driven by the evolution of powerful digital ICs. These controlled increasingly sophisticated PLLs and were the key enabling technology for complex techniques such as fractional-N synthesis.
PLLs are still key to the performance and wide frequency range of all kinds of signal generators and signal analyzers. However, as I mentioned in a recent post, direct digital synthesis (DDS) is coming of age in RF and microwave applications, and signal analyzers are the newest beneficiary.
A good example is the recently introduced Keysight UXA signal analyzer. DDS is used in the LO of this signal analyzer to improve performance in several areas, particularly close-in phase noise. The figure below compares the phase noise of three high-performance signal analyzers at 1 GHz.
The phase noise of the UXA signal analyzer is compared with the performance of the PXA and PSA high-performance signal analyzers. Note the UXA’s lack of a phase noise pedestal and significant improvement at narrow frequency offsets.
Phase noise is a critical specification for signal analyzers, determining the phase noise limits of the signals and devices they can test, and the accuracy of measurements. For example, radar systems need oscillators with very low phase noise to ensure that the returns from small, slow-moving targets are not lost in the phase noise sidebands of those oscillators.
A spectrum/signal analyzer’s close-in phase noise reflects the phase noise of its frequency-conversion circuitry, particularly the local oscillator and frequency reference. The phase noise of PLL-based LOs typically includes a frequency region in which the phase noise is approximately flat with frequency offset. This is called a phase noise pedestal and its shape and corner frequency are determined in part by the frequency response of the filters in the PLL’s feedback loop(s). The PLL’s loop-filter characteristics are adjusted automatically, and sometimes selectable by the analyzer user as a way to optimize phase noise performance in the most important offset region for a measurement.
With the DDS technology in the UXA, the absence of a pedestal means that improved performance is available over a wide range of offsets up to about 1 MHz. For very wide offsets, a PLL is used along with the DDS to get a lower phase noise floor from its YIG-tuned oscillator.
Despite its obvious advantages, DDS will not fully replace PLLs any time soon. DDS technology is generally more expensive than PLLs, requiring very high-speed digital-to-analog converters with extremely good spurious performance, and high-speed DSP to drive the DACs. In addition, PLLs still offer the widest frequency range, and therefore most DDS solutions will continue to include PLLs.