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2018

Get the most benefit from your DDR4 and next generation memory designs

 

DDR4 DRAM technology with fast data rates of 1600 MT/s and higher forced the industry to adopt high speed serial interface testing methodologies. Traditional setup and hold time tests are now replaced with eye diagrams and mask tests to account for bit error rate. Many DDR4 designers are still spending a lot of time trying to understand the specification and translate them into measurement methodologies. DDR5 is the next generation memory after DDR4, offering speeds up to 6.4 GT/s, and DDDR5 will present more design and testing challenges than DDR4. Learn how to better understand the DDR4 specification and its testing methodologies to help prepare yourself for the migration to DDR5.

 

When to Take the Leap - The Technology

There are many factors that drive technology migration. It helps to know the technology availability, the application, the speed, and the power requirement. There are three classes of volatile memory that are optimized for the different classes of applications – computer/server, graphics, and mobile applications. DDR4 is designed for the computing and server industry and has been around for quite some time with the fastest defined speed at 3.2 GT/s. JEDEC is currently working on the next-generation DDR memory, DDR5, to fulfil the request for faster data rates. It is anticipated that DDR5 will be able to operate up to 6.0 GT/s or higher. Graphics memory has the highest operating speed now at above 5.0 GT/s. GDDR6 is the latest graphics memory technology. The last class of volatile memory is the mobile DRAM, which is dominated by low power DRAM using DDR technology. LPDDR4 speed now surpasses DDR4 speed at 4.2 GT/s.

 

DDR technology trend.

Figure 1. DDR technology trend.

 

DDR4 Specification and Measurement Methods

JEDEC DRAM specifications are defined at the balls of the DRAM package. This is very different than other high-speed serial interfaces. For the longest time, DDR technology has adopted conservative design specifications. DDR technology uses a bi-directional, singled-ended, parallel bus. The specification is written to focus on interconnect and signal integrity characteristics with negative margin for timing budget. The industry over designs the parts to account for the negative timing margin.

 

One of the new measurements in DDR4 specification is receiver input masks. This one test would replace the traditional setup and hold time test. Memory timing specifications for previous DDR technologies like DDR2 and DDR3 were based on assumptions that the data capture will be error free if the data setup and hold time meet the specification. Lower data transfer rates in DDR2 and DDR3 have worked with these assumptions. This is not true for DDR4. DDR4 reflects the fact that random jitter and bit error rate are important parts of the specification, and changes have been made to the specification to help address these issues. Additionally, the specification now includes noise considerations such as the effect of noise-reducing eye openings. With all these specifications added to the standard, the lost margin can now be regained, and designers now can simplify their design and reduce design cycles, ultimately saving cost.

 

DDR4 receiver input mask.

Figure 2. DDR4 receiver input mask.

 

The Next Generation Memory

As previously mentioned, the next-generation DDR memory is anticipated to have data rates up to 6.5 GT/s. A potential consequence of running at these speeds is that the data eye could be closed at the receiver. This behavior is observed with other high-speed serial interfaces, such as PCI Express Gen 3. PCI Express Gen 3 implemented equalization on the receiver to open the eye for measurement and de-emphasis on the receiver side. The same methodology can be applied to DDR5 technology with several modifications. Memory is crosstalk dominant unlike PCIE, which is loss dominant. Memory is a single-ended, parallel bus and not a differential serial bus. The data bits in the DDR memory are not aligned. There is also no loopback mode in DDR4, so there is no way to perform receiver test. In DDR5, the receiver would need to tune itself via the training mode to minimize bit error rate. The specification describes what happens at the ball of the device. If you have an equalizer, the specification is written at the output of the equalizer, which is inside the DRAM die. You don’t know if you have an open eye in the die because you can’t probe inside the die directly. Hence, there is no eye mask specification at the ball. The eye would need to be opened using a decision feedback equalizer. The specification would model the impulse response of the channel. A decision feedback equalizer would back away impulse response effects of the channel, which would generate inter-symbol interference. These DDR5 measurements can be made using an oscilloscope with BER contour extrapolation. A loopback signal inside the memory would be required to figure out the receiver mask the memory would require.

 

Putting it All Together

Key components are required to ensure success of implementing DDR5 memory designs. Test equipment like oscilloscopes and bit error rate testers could help with some of the measurement challenges. Being able to make the measurements accurately would require advanced BGA probing capabilities, as the DRAM package is a BGA component. Parasitic loading is a big challenge to overcome when probing these high-speed buses. Early design stages could benefit from using modern simulation tools to model and optimize the system design. Power measurements are also a challenge, and the specification itself is not clear on how much noise is allowed in the power rail.

 

In summary, understanding the technology and specification helps you explore the best options for your design implementation. DDR4 memory is the first technology to adopt the receiver input mask concept. Understanding this concept allows you to quickly make meaningful measurements to ensure that the design works. DDR5 memory is the most advanced memory technology in its class. Measurement challenges associated with this new technology can be addressed using high-speed serial standard measurement techniques like equalization. A well-thought-out approach to the measurement requirement will enable high confidence in your memory system design.

Power Quality Determines the Performance of Your Device

Your product’s functional reliability is directly proportional to the quality of the DC power inside your product. Intuitively this makes sense: Stable DC supplies should not cause issues. Unstable DC supplies can cause unreliable performance.

 

In today’s products, IC density is increasing to provide more features faster. This means there are a larger number of smaller components packed onto each board, which makes your product more susceptible to the effects of poor power. To minimize the trouble power can cause, your design must convert and deliver DC power from the converters to the gates on the IC as effectively as possible. In other words, you want your design to have high power integrity, testing and verifying the integrity is crucial.

 

Tests Required to Validate Power Integrity

Evaluation usually consists of these four steps:

1. Analyze the output of your DC/DC converters without the rest of the circuit turned on.

  • This is to test the supply’s stability, looking for drift and PARD (Periodic and Random Disturbances).

2. Turn on your system and stress the supply under various operating conditions.

  • For example, test static and dynamic load to check the response and high frequency switching while keeping an eye out for transients and noise.

3. If your system has different power saving modes, you’ll evaluate your programmable power rails.

  • You want to ensure your supplies are reaching their intended level with the appropriate latency.

4. Lastly, run some (or all) of these tests again in a temperature chamber or accelerated life tester.

  • It is important to check operation in extreme environmental conditions and how your device will perform over time.

 

The Challenges of Making Power Integrity Measurements

For all the tests described above, you have a specific tolerance band. If the AC signals riding on your DC signal deviates too much, you have poor power integrity and your design is flawed. 

 

There are two major challenges to measuring your power integrity: noise and offset.

 

Noise

Noise from your oscilloscope, probe, and the connection to the DUT, are mixed in to your signal when you measure it. The result is that you don’t see an exact version of your signal on the oscilloscope screen. In light of this, make sure you are using a high-quality measurement system.

 

That means:

  • Choose an oscilloscope with low noise.
  • Choose a probe with low noise and 1:1 attenuation.
  • Connect to your DUT using as short of a lead as possible, with minimal to no probe-tip accessories.

 

Following these guidelines ensures you won’t mistake measurement system noise for power rail noise.

 

Offset

Viewing your AC swing can be difficult when your DC signal is large. To see the full signal on screen, you have to zoom out really far, but then you aren’t looking closely at the AC details. So, what do you do? Use a probe with support for power rail voltages. This is a probe with enough offset to be able to center the signal on screen without blocking DC so you can zoom in on the details of your waveform. What about a DC block, you ask?

 

Probe offset is better than using a DC block because:

1. Blocking capacitors not only block DC, they also block or filter low frequency AC.

 

  • This inhibits the ability to see drift, droop, sag, and other changes to the DC value of the power rail. These attributes are often critical to observe when your FPGAs and microprocessors turn on and off.

5V on a USB device measured with a DC block

Figure 1. 5V on a USB device measured with a DC block.

 

  • Probe offset passes all the AC content to the oscilloscope unfiltered.

5V on a USB device measured with probe offset

Figure 2. 5V on a USB device measured with probe offset.

 

  • In Figure 1, you can see the DC block shows what looks like a stable DC supply. In reality, the supply has some issues that become visible using the power rail probe in Figure 2. The issues can’t be seen with the DC block because it filters out the low frequency drift in the supply.

 

2. When using a DC block, the capacitor can discharge into your oscilloscope and blow out its front end. This is because the power rail you are measuring may exceed the input voltage of the oscilloscope, and the capacitor is being charged with that voltage. You may think you are protecting the oscilloscope from the voltage of your device, but if the capacitor discharges, all that energy will be sent into the front-end of your oscilloscope. This could be a costly repair.

 

3. DC blocks can make documentation of results tedious.

 

  • A DC block blocks all DC information from arriving to your oscilloscope. As a result, the oscilloscope will show the waveform centered at zero volts. Therefore, you need to use a DMM (digital multimeter) to see what the nominal value of the supply is and then manually type this information into any saved data or screen shots. Using a probe with offset means the oscilloscope knows the DC offset and can display things correctly, which makes record keeping easier. The DC offset is considered in any automated measurements or applications.

 

Additional Challenges – Loading and Bandwidth

 

Probe loading can cause your power supply to behave differently than it does without the probe connected or cause measurement errors like sag. So, you’ll also want to use a probe with very low loading.

 

You also want to choose a probe with high bandwidth. As I mentioned in the introduction, devices are now trying to do more at faster speeds. These increased speeds can introduce crosstalk on boards with small dimensions and lanes close together. And with the risk of crosstalk occurring, you’ll need to see transients, which requires high bandwidth. Having more bandwidth is also helpful for viewing high frequency supply noise, which can cause electromagnetic interference.

 

The Right Probe for Power Rail Measurements

Here is a summary of the tips provided above for overcoming power integrity measurement challenges:

 

Use a probe with:

1. Low noise

2. Support for popular rail voltages

3. Low loading

4. High bandwidth

 

If you need a specific product suggestion, use the Keysight N7020A or N7024A (New!) power rail probes.  They both meet the criteria suggested above and summarized below.

 

1. Low noise

  • The N7020A adds only 10% of the oscilloscope noise.
  • The N7024A adds only 30% of the oscilloscope noise.

2. Support for popular rail voltages

  • The N7020A has an offset range of ±24V.
  • The N7024A has an offset range of ±15.25V.

3. Low loading

  • The N7020A has an offset range of ±24V.
  • The N7024A has an offset range of ±15.25V.

4. High bandwidth

  • The N7020A has 2 GHz of bandwidth.
  • The N7024A has 6 GHz of bandwidth.

 

Power rail probe

 

Both probes work with Keysight Infiniium oscilloscopes, which have amazing signal integrity, low noise, and plenty of bandwidth. Additionally, they are compatible with special probing tips that help probe common surface mount capacitors packages.

 

Attribute

N7020A

N7024A

Probe bandwidth (-3dB)

2 GHz

6 GHz

Attenuation ratio

1.1:1

1.3:1

Offset range

± 24V

±15.25V

Input impedance at DC

50kΩ +/-2%

50kΩ +/-2%

Probe noise

0.1 * scope noise

0.3 * scope noise

Active signal range

± 850mV about offset voltage

± 600mV about offset voltage

Probe type

Single-ended

Single-ended

Included accessories

(orderable separately)

N7021A - Coaxial pigtail probe head (qty 3): 8”

N7022A - Main cable: 48”

N7023A – 350 MHz browser: 45”

Compatible, not included

N7032A 4 GHz browser for 0603 and 0805 packages (inch code)

N7033A 5 GHz browser for 0201 and 0402 packages (inch code)

1250-4403 Rotating SMA adapter

Output impedance

50Ω

50Ω

Extended temperature range

N7021A main cable, N7022A pigtail probe head: -40° to + 85° C