ErinEast

Schematic Challenge – Week 1

Blog Post created by ErinEast Employee on Mar 5, 2018

Prove yourself as an engineer! The Schematic Challenge is the perfect opportunity to test your skills. On March 5, 6, and 7, we will be posting a new schematic or problem-solving challenge. If you, as a community, are able to answer questions 1, 2, and 3 correctly by Thursday, March 8 at 11:59 PM MST, we will add three 1000 X-Series oscilloscopes to the overall Wave 2018 giveaway! Answers should be posted in a comment on the #SchematicChallenge posts on the Keysight Bench or RF Facebook pages. Work with your family, friends, coworkers, or fellow engineers in the Wave community to solve these problems. If you haven’t already, be sure to register for Wave 2018 at wave.keysight.com.

 

Question 1:

By Ryan Carlino

 

Status: SOLVED! (minimum of 8 bits)

 

Week1 Question 1 SchematicYou need to design a circuit to determine the resistance of an unknown ID resistor.
A voltage divider provides a bias that creates a voltage at the input of an ADC.
You’d like to be able to distinguish between a 15K and 20K ID resistor.
The ADC has a 0.5% internal 3.3V reference. The resistors are all 1%.
What is the minimum number of bits of resolution that the ADC needs in order to have at least 10 codes (LSBs) between a 15K and 20K resistor?

 

Question 2:

By Ryan Gillespie

 

Status: SOLVED! ( V(d)=(0.72 - 0.13i) V )

 

Given the doubly terminated transmission line, calculate the voltage at d = 100 µm.

Hint: First you may want to solve for Zo, Wave Speed, Wavelength, V(x) and I(x)

Your answer should be in the form of V(d) = ( # + #i )  where # are the numerical answers.

 

 

 

Useful formulas:

 

Question 3:

By Patrick Mann

 

Status: SOLVED!

 

Given the block diagram in figure 1, is the additional explicit trigger input shown in blue in figure 2 required? Select the correct answer and post the respective letter on the Keysight Bench or RF Facebook pages:

 

  1. The explicit trigger is not required since the sampling oscilloscope can trigger off the data.
  2. The explicit trigger is required since the sampling oscilloscope cannot trigger off the data.
  3. The explicit trigger is not required because the precision waveform analyzer module can recover a clock and feed it to the sampling oscilloscope’s trigger circuitry.
  4. The explicit trigger is required because the precision waveform analyzer module cannot recover a clock and feed it to the sampling oscilloscope’s trigger circuitry.
  5. The explicit trigger is not required because the external time reference feeds into the sampling oscilloscope’s trigger circuitry.
  6. The explicit trigger is required because the external time reference feeds into the sampling oscilloscope’s trigger circuitry.

 

Figure 1: Precision Waveform Analyzer module (blue) and sampling oscilloscope mainframe block diagram (green)

 

Figure 2: Connection diagram of a sampling oscilloscope and module (left) to a pseudorandom binary sequence (PRBS) generator (right)

Outcomes