# Power Integrity Analysis, The Logical Next Step After Making Sound Power Integrity Measurements

Blog Post created by KennyJ on Nov 1, 2017

Recently I was visiting the SIPI lab (Signal Integrity and Power Integrity) of a large corporation showing them how to make some solid power integrity measurements that they could trust (check out this application note if you’d like some tips). We had just finished making some ripple and noise measurements on one of the key supplies inside their system (using our power integrity analyzer) when the PI Lab manager shared a thought with us. He said “You know, I am a bit of a perfectionist. There is always more work we could do to clean up the supplies but I have limited resources, so I wish there was a button I could push that would tell me if it is worth it or not. What can I gain if I clean up the DC supplies.” I think many folks working on power integrity (PI) have this same thought. “Before I model, simulate, redesign, re-layout, fabricate, load and test a new revision, I’d like to know if there is a lot or little to be gained by cleaning up the DC supplies.

The issue that the above group was struggling with was power supply induced jitter (PSIJ). PSIJ is frequently the biggest source of clock/data jitter. The delay through a device varies as a function of the voltage applied to that device. Therefore, a system with very little DC supply noise will have very little PSIJ and conversely for a system with a lot of supply noise. The difficult part is getting an idea how much PSIJ your supplies are causing, because it varies from supply to supply, from device to device and target to target. To illustrate PSIJ, consider the example in Figure 1 where we are probing the 1.1V supply to an FPGA and one of the data lines from the FPGA. Initially, the supply has about ±5% Vpp ripple, noise and transients on the supply. We built an eye diagram of the transitions on the data line and could see that the eye width was around 70ps. Next, we did the heavy lifting and cleaned up the supply so that it is rock solid with <1% Vpp ripple, noise and transients. Again, we built up an eye diagram on the FPGA data line and found the eye width increase to about 115ps or about a 55% increase. The only thing that had changed was the amount of noise on the power rail.

Figure 1: The effects of power supply noise on the data lines of an FPGA

Don’t be fooled into thinking that this problem is reserved for those working on very high-speed designs. I have seen power supply induced data corruption on a little IoT device that is only clocked at a few MHz’s If you’d like to see this example, check out this video.

Understanding the impact of power supply noise on data lines, sensors, clocks, displays, cameras, et cetera can be difficult. Some users who have been doing PI for a long time may have a ‘gut feel’ that they trust but even these folks would find comfort in some ‘hard data’ to back up their intuition. Traditionally, the way to find answers to this question has come from doing extensive modeling and simulation—power-aware, signal integrity simulations. This approach is usually reserved for the few who work for institutions that can afford the simulation tools and the dedicated staffing to operate these tools.

Worry not, there is an answer for the rest of us. It is even as simple as pushing a button like our friend the SIPI lab manager wished for (okay, truth be told, I think it is about 3 or 4 mouse clicks not one but close enough).  The new Keysight N8846A Power Integrity Analysis application. To give you an idea of how the PI Analysis application can be helpful let’s return to our FPGA example. The setup is the same as our previous example except for this time we use the N8846A PI Analysis application to estimate what the eye width would be without the negative effects of power rail noise (we didn’t do anything to clean up the supply this time). Figure 2 below shows the results from the N8846A. You’ll notice the applications estimate for eye width with a clean supply matches what it really was when we cleaned up the supply.

Figure 2: The results from the N8846A Power Integrity Analysis Application. Note that the prediction from the application matches the results from Figure 1 where the supply was physically changed.

The N8846A PI analysis application lets users define a dc supply as either a victim of or an aggressor to, one other periodic transitioning signal and predicts the amount of adverse interaction involved. In this way, users can see what their dc supply and/or toggling signals would look like if they were immune to the negative effects of each other. With this insight, users can make informed decisions about what, if any, next steps they would take to clean up the dc supplies. This is the “button” that our friend at the SIPI lab was asking for.