KeysightOscilloscopes

Advanced Transmitter Measurement Techniques for PCI Express (PCIe) 4.0 at 16GT/s

Blog Post created by KeysightOscilloscopes Employee on Oct 25, 2017

Written by Rick Eads

The Need for a 16GT/s PCIe Interconnect

PCI Express represents one of the most successful computer interconnects yet devised and helped to enable high-speed connections between external devices such as displays and storage adapters to the internal CPU of the computer.  As networking speeds have increased (datacenter), as display resolution has increased (4K streaming) and as disk drive capacity and speed has increased (cloud computing), the need for an improvement in the speed of a host adapter to the CPU has also driven the development of the next generation of the PCI Express 4.0 Standard.  PCie 4.0 technology doubles the bandwidth of the previous generation of PCie 3.0 devices as PCIe 4.0 is able to achieve throughput of nearly 32 GBytes/s for 16 lanes.

 

PCie 4.0 technology doubles the bandwidth of the previous generation of PCie 3.0 devices as PCIe 4.0 is able to achieve throughput of nearly 32 GBytes/s for 16 lanes.

What’s New about the PCIe 4.0 standard versus PCie 3.0?

The biggest improvement brought by the PCIe 4.0 standard is a doubling of the speed to 16GT/s per lane.  Nevertheless, there are additional changes to the PCIe 4.0 specification versus the Gen3 Spec that is worth noting.  Due to the higher data rate, the maximum channel loss accommodated by the PCIe 4.0 standard is approximately -28dB, which implies a maximum channel length of about 12” (or 25cm) with a single CEM class connector.  To accommodate channels longer than 12”, the PCie 4.0 specification provides protocol and electrical requirements for a retimer device which can be used to extend the PCIe 4.0 channel and can help to accommodate multiple connector topologies.  Another new feature of the PCIe 4.0 specification has been the addition of a lane margining capability.  Lane margining allows for in-band (L0) based adjustment of the receiver sampling point which allows for an estimation of eye width, and an optional mode also allows for voltage margining which may provide information regarding eye height.  This feature is intended to help system integrators determine product readiness for shipment.

 

Testing PCIe 4.0 Card Electromechanical (CEM) Devices

While the PCI Express 4.0 BASE specification is nearing 1.0 status, it primarily is written to accommodate new silicon or ASIC devices operating at 16GT/s.  PCI Express also accommodates a system specification referred to as the Card Electromechanical (CEM) specification.  This is the specification that is used at PCISIG compliance workshops to determine if motherboards and add-in cards are compliant to the PCIe 4.0 application.  To accomplish this, the PCISIG has commissioned the development of both new CEM test fixtures and new test software.  As of this writing, both are still in development but are being used in US-based compliance workshops since April 2017.  One new aspect of testing CEM devices under the PCIe 4.0 specification is the addition of an external physical ISI channel that is chosen/calibrated to ensure the maximum CEM channel loss is achieved.

 

                      

Fig 1: Prototype CEM Test Fixtures (CBB4 and CLB4)

Oscilloscope bandwidth requirement

The minimum oscilloscope bandwidth required for PCI Express 4.0 is 25GHz.  As the minimum eye height is 15mV, it is important to utilize real-time oscilloscopes with the lowest noise floor to minimize error and to maximize the measured margins.

 

The minimum oscilloscope bandwidth required for PCI Express 4.0 is 25GHz.  As the minimum eye height is 15mV, it is important to utilize real-time oscilloscopes with the lowest noise floor to minimize error and to maximize the measured margins.

Making PCI Express BASE spec transmitter measurements

Keysight’s new N5393F PCI Express transmitter test application provides step-by-step instructions to guide you through the process of configuring the test setup, selecting the tests and connecting the signals to the oscilloscope.   The N5393F supports PCI Express 4.0 testing at 16GT/s for BASE spec tests and also supports legacy testing under the PCIe 3.0, 2.0, and 1.0a/1.1 standards.  The N5393F test provides visual connection aids to facilitate the connection of your DUT to the oscilloscope and with optional software also integrates the ability to de-embed test fixtures, provide DUT automation for test mode selection (2.5G, 5G, 8G).

 

                 

Figure 2: PCI Express 4.0 BASE spec connection diagram including replica channel for de-embedding

 

                  

Figure 3: Keysight N5393F PCI Express automated test application for the oscilloscope showing the PCIe 4.0 BASE specification tests for 16GT/s validation

Summary

Keysight has been a consistent and valued contributor to the development and authorship of the PCI Express specification since the initial 1.0a draft and continues to provide valuable guidance to the PCISIG for transmitter testing, receiver testing, and channel testing and characterization.  Other optional tools such as the N5465A InfiniiSim Waveform Transformation toolset and N5461A equalization application can provide deep analysis and debug capability. In addition, Keysight has other comprehensive test solutions from design simulation to physical layer testing that includes transmitter, receiver and channel for the PCI Express 4.0 standard as well as previous generations of PCIe.

Outcomes