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2017

 Oscilloscopes are used to measure and evaluate a variety of signals and sources. They also play a major role in both design and manufacturing, providing a visual display of voltage over time. Many times oscilloscope users need more than a visual representation and want to validate the quality and stability of electronic components and systems. The Keysight Technologies mask test option, DSOX6MASK, for InfiniiVision Series oscilloscopes can save you time and provide pass/fail statistics in seconds. The mask test option offers a fast and easy way to test your signals to specified standards, as well as the ability to uncover unexpected signal anomalies and glitches. Mask testing on many industry oscilloscopes is based on software-intensive processing technology, which tends to be slow. Keysight’s mask test option is based on hardware-accelerated technology performing up to 270,000 real-time waveform pass/fail tests per second. This makes your testing throughout orders of magnitude faster. This Keysight InfiniiVision ground breaking Mask Technology is supported by their industry leading highest sampling rate at 1,000,000 waveforms per second allowing for improved display quality to catch subtle waveform details such as noise and jitter.

 

Mask Testing

Figure 1 shows a pulse-shaped mask using an input signal standard. You can easily specify horizontal and vertical tolerance bands in either divisions or absolute volts and seconds. You can set up the mask test to run continuously in order to accumulate valid pass/fail statistics. In this example, an infrequent glitch was quickly detected. In just six seconds, the mask test statistics show that the scope performed the pass/fail mask test on more than 1,000,000 waveforms and detected just two errors for a computed error rate of 0.0002%. In addition, you can see that this particular signal has a sigma quality relative to the mask tolerance of approximately 6.1 σ.

Mask Testing

Figure 1 - Mask testing uncovers an infrequent signal anomaly

 

Importing an industry-standard mask -

Figure 2 shows testing results of an industry standard imported eye-diagram mask. This particular polygon-shape mask is based on a published standard and was created using a simple text editor.

 Mask Testing

Figure 2 - Testing an eye-diagram with an imported industry standard mask.

 

You can also set up masks around areas of the signal that should be off-limits. That way you do not need a perfect signal; just an understanding of how a signal looks when it functions correctly. Mask testing provides more reliability than testing individual attributes because the entire signal can be evaluated against a correct signal to find glitches and/or errors. As a result, mask testing saves time and money in design and manufacturing and ensures customers receive higher-quality products sooner.

 

Keysight Mask Test Functions include -

  • Automatic mask creation using input standard
  • Easily download multi-region masks and setups based on industry standards
  • Detailed pass/fail statistics
  • Test to high-quality standards based on sigma
  • Multiple user-selectable test criteria

 

When setting up your specific mask test criteria, you can choose from multiple options including:

  • Run forever (with accumulated pass/fail statistics)
  • Run until a specified number of tests
  • Run until a specified time duration
  • Run until a maximum ideal sigma standard
  • Stop-on-failure
  • Save-on-failure
  • Print-on-failure
  • Trigger out-on-failure

 

Low Noise –

Lower inherent vertical noise is key when making quality and precise mask tests. Vertical noise can cause random increases (spikes) in all areas of the signal, including trigger timing issues. Figure 4 below shows test results in just 6 seconds, capturing 3 elusive failures out of one million waveforms sampled. A consistent trigger point is vital to prevent jitter and drift of the waveforms. If a signal drifts outside the mask limits due to noise and/or trigger jitter, mask testing will analyze the oscilloscope-induced error components as a failure, thereby corrupting the test results. A low noise floor is essential to attain the precision and reliability of Six Sigma testing.

 Mask Testing

Figure 3 - Mask testing to 6.2 sigma resolution takes only seconds using an InfiniiVision scope with a mask test rate of 270,000 waveforms/s

 

Conclusion –

Not only does Keysight provide the fastest, low-noise mask testing performance in the market, but the mask test application on InfiniiVision scopes also has a variety of features for customizing your measurements. The Keysight mask testing software allows you to setup the mask test to run for a specified time, until a certain sigma threshold is reached, continue running upon a failure, stop on a failure, or save the data on a failure. This allows you to run a complete six sigma test in around one second. If a failure occurs the waveform can be set to automatically stop or saved for viewing and later analysis work. The capability to assure the quality of products to Six Sigma in 1.1 seconds saves time and effort in R&D and manufacturing. In R&D environments, engineers can test signals they are developing through many waveform repetitions spending less time but still ensuring signal stability. The more waveforms they can test, the more confidence they have that the design functions correctly. In manufacturing environments engineers must test signals to ensure customers receive reliable products. Your company can save manpower hours and can invest the capital in profitable initiatives, such as new product design. At the same time, customer satisfaction will increase as you produce high-quality products and move them quickly into the market.

Here in Keysight Oscilloscopeland we talk a lot about our ASICs (application specific integrated circuits). But why? Who cares about the architecture of a cheap oscilloscope? All that matters is how well it works, right? We agree. That’s why we design and use oscilloscope-specific chips for all our scopes.

 

How, though? Custom ASICs don’t just materialize out of thin air, it takes years of planning and R&D effort. Here’s a high level look at what it takes to make an ASIC.

 

The making of an ASIC

There are several different steps (and teams) involved in the creation of an ASIC. Before anything is started, there must be a long-term product plan – what do designers want to have 5-10 years down the road? Future products will have new specs or features that will sometimes warrant an ASIC. To make that decision, product planners meet with the ASIC planners.

 

An oscilloscope's ADC ASIC

A custom 8 GHz oscilloscope ADC, used in Keysight S-Series Infiniium oscilloscopes.

 

Planning

First up is the planning team. They ask “what chips do we need to have in a few years? – Let’s make that.” And, “what will be available off-the-shelf in a few years? - Let’s not make that.” The planners will also make cost vs. performance trade-off decisions (device speed, transistor size, power consumption, etc.).

 

Also, ASICs generally fall into one of two categories: digital or analog. Analog chips are essentially signal conditioning chips designed to massage signals into a more desirable form. Digital chips are essentially streamlined FPGAs, designed for processing data inputs and providing coherent data outputs. For example, our MegaZoom ASICs take data from an oscilloscope’s front end circuitry + ADC and output waveforms, measurements, and other analytics. 

 

processor chips on 1000 X-Series scope

Fig 1: The Keysight-custom ADC and processor chips on the InfiniiVision 1000 X-Series oscilloscopes

 

It's worth noting there's a third type of ASIC - a mixed signal ASIC like an ADC (Fig 1.)

 

Digital ASICs

 

Now, let's take a closer look at process of creating digital ASICs, like the MegaZoom processor in the InfiniiVision oscilloscopes.

 

Front-end/RTL design

Once the chip is well defined by the planning, the front-end team gets to work. They are responsible for the “register-transfer level” (RTL) design (and typically spend their days with Verilog or VHDL). Their goal is to create a functioning digital model of the chip, but not a physical model. The RTL team is ultimately responsible for taking the chip design specs and turning it into actual logic and computation models. To do this, they use digital design components/building blocks and techniques like adders, state machines, pipelining, etc.

The RTL team is ultimately responsible for taking the chip design specs and turning it into actual logic and computation models.

 

As the front-end team is working, there’s also test team that works to check the RTL for errors. The goal is to try to avoid situations like the infamous Pentium FDIV bug that cost Intel nearly $500 million in 1995.

 

Once the RTL is proven to be functional by the test team, it is synthesized into a netlist. This essentially means that the RTL is converted from logic blocks into individual logic gates. Today, software handles this, but historically it was done by hand and engineers used truth tables and Karnaugh maps. The netlist is then run through a formal verification tool to make sure it implements the functionality described in the RTL before being passed to the back end team. 

 

Back-end

Once the logic is verified, it’s time to physically implement the chip. This is typically known as “floorplanning.” Floorplanners use crazy-expensive software (hundreds of $k) to place the RTL onto the chip footprint. In reality, the back end team generally gets early versions of the netlists so they can get a head-start on floorplanning.

 

The back end work begins with an overall placement of design blocks on the chip. The general workflow for the back-end team is:

 

  1. Floorplanning
  2. Individual gate placement
  3. Clock tree building
  4. Routing
  5. Optimizing
  6. Static timing analysis

For the chip to function properly, gates involved in the same computational processes should be close together. Also, designers have to make sure that power can be distributed properly throughout the chip.

 

A clock tree is a clock distribution network designed to make sure the clock reaches each of the gates at the same time. If clock edges arrived up at different times to different parts of the chip, it could cause painful timing errors. Sometimes, designers also intentionally add some clock skew to keep an edge from arriving too soon.

 

The back end work begins with an overall placement of design blocks on the chip.

 

Once placement is complete, software then auto-routes the connections between gates. You’re probably familiar with the phrase “never trust the autorouter.” In this case though, that’s really the only option unless you want to manually route hundreds of thousands (or millions) of connections.

 

Oscilloscope acquisition board

Fig 2: Routing of an oscilloscope acquisition board

 

Finally, an ongoing concern throughout the whole process is whether or not the design is actually manufacturable. This is known as DRC (design rule checking). Basically, this is a set of rules designers provide to the software to tell it what architectures (aka physical shapes) are and aren’t physically possible. Then, there's a layout vs. schematic check (LVS) to verify that the physical geometries actually implement the desired circuitry.

 

Tape Out

Once the front end and back end teams are done, it’s party time. This stage, known as “tape out,” is when the final design is prepped for production. Massive files are sent to the fab, who creates photomasks for each layer of the ASIC. It’s not unusual for there to be 30-50 masks for a single chip.

In the final stage, known as “tape out,” the final design is prepped for production.

 

Manufacturing

Once the masks are created, a number of different techniques are used to manufacture the chip. Usually a combination of photolithography, acid baths, ion implantation, furnace annealing (baking), and metallic sputter deposition is used. Each silicon wafer holds dozens (or hundreds) of identical layouts that will later be cut up into discrete chips.

 

The completed wafer is then tested for manufacturing errors. Depending on the size of the wafer and complexity of the process, planners can usually predict the failure rate of each chip. Microscopic anomalies, like a speck of dust under mask, can cause a chip to fail. “Scan testing” is used to check each gate. Scan testing consists of applying a pre-determined pattern of signals that will test every single gate on the chip, and each chips’ output is compared to the expected output. Each die is tested, and the chips that pass are sent on to be packaged.

 

Packaging

Good dies are then placed into packages and tested again. The packaging team typically designs a custom package for the die, and needs to consider signal integrity, cost, thermal regulation, and reliability. Often, we at Keysight will re-design the package of an existing ASIC using updated technology to reduce hardware cost and improve reliability of our oscilloscopes.

The packaging team typically designs a custom package for the die, and needs to consider signal integrity, cost, thermal regulation, and reliability.

For example, the ADC on our inexpensive oscilloscopes is the same ASIC used in some legacy oscilloscopes, but by improving the packaging over time we’ve reduced the package cost by nearly 5x. Thanks to that cost reduction, what was once used for only for a top-of-the-line oscilloscope we can now use in our cheap oscilloscope.

 

Support Circuitry

Once a chip is manufactured, tested, and packaged, it still needs to be surrounded with support circuitry. For example, what good is an op amp if you never configure it with resistors? But, that’s a topic for another blog post.

 

How it’s made

So, while you wouldn’t want to use this description to go design your own ASIC, you should now have a better understanding of what it takes to produce an ASIC. It’s a lot of work, but the benefits they offer compared to FPGAs are often worth the investment. For any given Keysight oscilloscope, we use a few different ASICs. We use analog ASICs for the front end, a custom low-noise ADC, and often a custom processor as the brain of our oscilloscope. While this comes with a fairly large non-recoverable engineering expense (NRE), being able to use the same chip in our $45,000 oscilloscopes and our $450 oscilloscopes earns our oscilloscopes special place on the budget-conscious engineer’s bench.

Lab benches are many times cluttered with multiple pieces of test equipment. Keysight’s InfiniiVision Oscilloscopes are equipped with a built in digital voltmeter, frequency counter and totalizer giving the oscilloscope user additional measurement options that can reduce the amount of test equipment needed. In addition, when you only measure the frequency of a signal, you rarely get the whole story. A repetitive signal can have spurs, intermittent spikes and noise that you need to see during design and or debug. The oscilloscope counter will show you all these attributes in addition to the frequency in one screen shot giving you the “big” picture. Keysight InfiniiVision oscilloscopes include both a 3 digit voltmeter (DVM) and a 5-10 digit Integrated Counter depending upon the oscilloscope model number (Figure 1 below).

 

 

Figure 1 – Functionality, options and specifications across the Keysight InfiniiVision family of Oscilloscopes

 

Digital Volt Meter

The DVM and Integrated Counter operate through the same probes as the oscilloscope channels. However, these measurements are decoupled from the oscilloscope triggering system measuring 100 points per second. This flexibility allows engineers to make DVM and triggered oscilloscope measurements with the same connection. DVM results are presented with an always-on seven-segment display keeping these quick characterization measurements at the engineers' fingertips. You get the added flexibility of measuring five types of DVM measurements depending upon your application: Peak-Peak, AC rms, DC, and DC rms. As a user you should also note that the oscilloscope DVM is designed for quick rough measurements as needed in design or debug and not meant to replace exact measurements you would get from a calibrated external DVM.

 

Standard 5 digit counter resolution

The traditional oscilloscope counter measurements offer only five or six digits of resolution, which may not be enough for the most critical frequency measurements are being made. With a 10 digit counter you can see your measurements with the precision you would normally expect only from a standalone counter. The Keysight integrated counter’s ability to measure frequencies up to a wide bandwidth of 3.2 GHz, allows it to be used in many high-frequency applications. This integrated hardware counter allows users to make much more accurate frequency measurements on signals. 4 digits is 1 part in ten thousand, or ~0.01% of the displayed number. In addition, relative to an industry standard oscilloscope frequency measurement, the Keysight counter measurement is designed to be very easy to use. It uses the trigger level of the oscilloscope as the trigger level for the counter independent of the cycles shown on the screen.

 

Up to 8 to 10 digit resolution with external time base

If an external 10MHz reference is used, the counter is as accurate as the externally fed 10MHz signal and the measurement resolution is increased. The 10MHz REF BNC connector on the rear panel is provided so you can supply a more accurate clock signal to the oscilloscope. To drive oscilloscope’s time base from external clock reference, connect a 10MHz square or sine wave reference signal to the 10MHz REF BNC input on the rear panel and go to the Utility -> Options ->Rear Panel menu and select Ref signal mode to 10 MHz input. The working 10MHz input voltage is 180mV to 1V in amplitude, with a 0V to 2V offset. To get the highest resolution, the time/div setting should be at 200mS/div or slower. With this setting, the resolution is increased up to 8 digits, which is what would be displayed if an external 10MHz reference is used. When the internal reference is used, the oscilloscope displays counter measurement in 5 digits. The counter measurements can measure frequencies up to the bandwidth of the oscilloscope.

 

Accuracy

Basically, the counter is as accurate as the time base reference that is used.  The oscilloscope’s time base uses a built-in 10MHz reference that has an accuracy of 1.6 ppm to 50 ppm depending upon the oscilloscope model number. This means that the number displayed is within 0.00016% to 0.0050% respectively of the actual signal measured. For example, if you are making a counter measurement of 32,768 Hz signal using a model 6000X with 1.6 ppm accuracy, you are measuring the signal at ~0.05 Hz accuracy (see calculation below).

32,768 Hz x 1.6 ppm (0.00016%) = ±0.0524288 Hz

 

Totalizer

The totalizer feature of the DSOXDVMCTR counter option adds another valuable capability to the oscilloscope. It can count the number of events (totalize), and it also can monitor the number of trigger-condition-qualified events. The trigger-qualified events totalizer does not require an actual trigger to occur. It only requires a trigger-satisfying event to take place. In other words, the totalizer can monitor events faster than the trigger rate of an oscilloscope, in some cases as fast as 25 million events per second. Keep in mind that the number of events is a function of the oscilloscope’s hold off time.

 

Summary

The voltmeter and counter functions discussed in this article are just two of the “6 instruments in one oscilloscope” of the Keysight InfiniiVision family. The six instruments are the oscilloscope, 16 digital channels (mixed signal), serial protocol analyzer, Dual channel 20 MHz function/arbitrary waveform generator, 3-digit voltmeter and 5 to 10-digit counter with totalizer.

 

The voltmeter operates through the same probes as the oscilloscope channels. However, the DVM measurements are made independently from the oscilloscope acquisition and triggering system so you can make both the DVM and triggered oscilloscope waveform captures with the same connection.

 

Traditional oscilloscope counter measurements offer only five or six digits of resolution. While this level of precision is fine for quick measurements, it falls short of expectations when critical frequency measurements are needed. With the integrated counter within the five Keysight oscilloscope families summarized in Figure 1, you can select between 5 and 10 digit counter options and see your measurements with the precision you would normally expect only from a standalone counter. Because the integrated counter measures frequencies up to a wide bandwidth of 3.2 GHz, you can use it for many high-frequency applications as well

Keysight continues to invest in the very popular InfiniiVision X-Series oscilloscopes with new oscilloscope models, new options, and customer-requested enhancements. Every 6 to 8 months, Keysight releases new firmware that our customers can download into their InfiniiVision scopes at no cost. The latest release of firmware (version 7.10) for the InfiniiVision 3000T, 4000, and 6000 X-Series oscilloscopes includes three new licensed “pay for” options as well as several FREE upgrades/enhancements including the following:

 

  • User-definable Manchester/NRZ Trigger & Decode Option
  • Frequency Response Analyzer (FRA) Option
  • CXPI Trigger & Decode Option (new on 6000X, existing on 3000T & 4000)
  • DVM/Counter Option – Now standard!
  • Education Training Kit Option – Now standard!
  • On-screen grid scaling factors – Standard!
  • FFT RF power measurements -Standard!

 

 

User-definable Manchester/NRZ Trigger & Decode Option (DSOXT3NRZ, DSOX4NRZ, & DSOX6NRZ)

 

Keysight’s InfiniiVision X-Series oscilloscopes support triggering on and decoding a broad range of today’s most popular serial bus protocols including I2C, SPI, UART, CAN, USB, etc.  But what happens if you are working with one of the less popular — or perhaps proprietary — serial bus protocols that isn’t supported? Available now on InfiniiVision 3000T, 4000, and 6000 X-Series oscilloscopes is a “user-definable” Manchester- & NRZ-encoded serial bus option. This new trigger and decode option allows you to define the specifics parameters and structure of your particular serial bus including:

 

  • Encoding type (Manchester or NRZ)
  • Baud Rate
  • Start edge
  • # of Synchronization bits
  • Word size
  • Header field size
  • Data field size
  • Trailer field size
  • Decode Base (binary, hex, ASCII, or unsigned decimal)

 
Also available are three new application notes that provide step-by-step instructions on how to set up triggering and decoding for three specific Manchester-encoded serial bus measurement applications including the automotive PSI5 sensor bus, automotive RF-modulated key fob signals, and NFC-F signals. Figure 1 show an example of triggering on and decoding the automotive PSI5 sensor bus, which is often used in airbag systems.

 

Figure 1: Triggering on decoding the Manchester-encode PSI5 sensor bus using Keysight’s user-definable serial bus option.

 

In the above PSI5 measurement example, after detecting the 2-bit Start field, the scope triggered on and decoded a 10-bit payload field followed by a parity bit. The scope also automatically detected a Manchester timing error in the frame that immediately followed the trigger frame (155h). To learn more about triggering on and decoding the PSI5 serial bus, download the new application note on this topic.


 


Figure 2 above shows an example of decoding automotive key fob signals.

 

Decoding RF-modulated key fob signals requires hardware digital demodulation. The new application note on this topic shows you how to capture the RF signal with a “sniffer” probe, how to demodulate the captured signal in hardware, and then how to decode each “code-hopping” RF burst. To learn more about how to set up the scope to demodulate and then decode RF-modulated key fob signals, download the new application note on this topic.


  
Figure 3 above shows an example of decoding NFC-F signals.

 

With NFC-F signals, the scope automatically demodulates the captured RF-modulated waveform if based on a baud rate of either 212 kbps or 424 kbps. When the new Manchester trigger and decode option is used along with the recently-introduced NFC automated test software, the designer of NFC-enabled device now has a very powerful set of debug and test tools. To learn more about how to set up the scope to decode NFC-F signals, download the new http://literature.cdn.keysight.com/litweb/pdf/5992-2337EN.pdf on this topic.

 

 

Frequency Response Analyzer (FRA) Option (DSOXT3FRA, DSOX4FRA, & DSOX6FRA)

 

Using the InfiniiVision oscilloscope’s built-in function generator (WaveGen), these scopes can now perform automatic frequency response analysis (Bode gain & phase plots) as shown in Figure 4 below.

 

 

Figure 1: Triggering on decoding the Manchester-encode PSI5 sensor bus using Keysight’s user-definable serial bus option.

 

Frequency Response Analysis (FRA) is often a critical measurement used to characterize the frequency response (gain & phase versus frequency) of a variety of today’s electronic designs including passive filters, amplifier circuits, and negative feedback networks of switch mode power supplies (loop response). Engineers typically use network analyzers or standalone low-frequency FRAs to perform these types of measurements today. To learn more about the new FRA option, download the data sheet.

 

 

Free InfiniiVision Enhancements with Firmware Upgrade

 
In addition to the new “pay-for” options listed above, there are also free enhancements available for InfiniiVision X-Series oscilloscopes with an upgrade to the latest firmware (v7.10). The built-in DVM and hardware counter option shown in Figure 5 will no longer be an option. These measurement capabilities will now be standard features of all InfiniiVision oscilloscopes.

 

 

Figure 5: The DVM/HW Counter option is now a standard feature in all InfiniiVision X-Series oscilloscopes.

 

The measurement example shown above shows output ripple riding on top of a 5 V dc output from a switch mode power supply (SMPS) with a switch rate of approximately 2 MHz. The scope’s built-in DVM shows that the actual DC output measures 4.97 V and the actual switching rate is 2.0112 MHz as measured by the 5-digit hardware counter.

 

Another new free enhancement is on-screen vertical and horizontal grid scaling factors along the left vertical axis and lower horizontal axis, which is also shown in Figure 5. This has been a very popular feature in Keysight’s higher-performance Infiniium oscilloscopes. Labeling each grid with scale factors can help you quickly estimate voltage levels and timing of your signals. 


In addition to making the DVM/Counter option standard, the education training kit (EDK) option is now standard as well on all InfiniiVision 3000T, 4000, and 6000 X-Series oscilloscopes with the latest firmware upgrade. Using the built-in training signals shown in Figure 6 along with available online training guides, users unfamiliar with the operation of Keysight InfiniiVision oscilloscopes can get up-to-speed quickly. To learn more about the EDK training kit and to download the training guides, go to the InfiniiVision http://www.keysight.com/en/pd-1952427-pn-DSOXEDK/educators-training-kit-for-infiniivision-2000-and-3000-x-series-oscilloscopes?cc=US&lc=eng webpage.

 

 

 Figure 6: The education training kit (EDK) is now standard and includes multiple built-in training signals and online training guides.

 

Also available at no cost in this latest firmware release are new automatic RF power measurements that can be performed on FFT math functions. Figure 7 shows an example of an Adjacent Power Ratio measurement performed on an RF-modulation sideband measurement. Other new RF measurements include Channel Power, Occupied Bandwidth, and Total Harmonic Distortion (THD).

 

Figure 7: New FFT analysis measurements.