The second the probe is connected to your device your signal begins a grand journey to the center of the scope. It has to pass through five phases in order to complete its journey to the center, then back up to the surface. First the signal has to find its way to the front of the scope through the probe. Then, once it enters the scope, it has to go through an attenuator, DC offset, and amplifier before it can reach the center. At the center, the signal goes through an analog to digital converter. In order to make its way back to the surface of the scope, it must venture to find the display DSP. Along the way, it finds evidence that signals have been here before. The timebase and acquisition blocks show that previous samples of signals have been collected. Once the signal passes through these two blocks, it will finally be displayed on the surface of the scope. Let’s learn a little bit more about everything your signal encounters along this journey.
Your signal’s journey begins with traveling from your device through a series of resistive and capacitive components inside the probe. The attenuation specification of your probe will determine what resistive components are inside. Most standard passive voltage probes that come with DSO scopes have a 10:1 attenuation ratio. This type of probe would have a 9 MΩ probe tip resistor in series with the scope’s 1 MΩ input impedance. This would make the resistance at the probe tip 10 MΩ, which means that when your signal travels through the probe and reaches the scope’s input, it will be 1/10th of the voltage level that it was when it entered the probe at the tip from your device. This means that the dynamic range of the scope measurement system has been extended because you can now measure signals with 10x higher amplitude as compared to signals you could measure using a 1:1 probe. Also, this 10:1 passive probe ensures a high input impedance at the probe tip which will eliminate any loading on your device. Loading will change the way your device behaves, and we don’t want that.
Next the signal enters the scope to begin the first phase of processing, analog input signal conditioning. There are three stages to this conditioning process which are all done in order to scale the waveform correctly to be within the dynamic range of the analog-to-digital converter (ADC) and the amplifier. The processing done in these stages is dependent on what the V/div and offset settings are, which ultimately depends on whether you are measuring a low level or high level signal. First, the signal is scaled in the attenuator block, which is a network of resistor dividers. If you have a high level input signal, then the signal will be attenuated, or reduced. If you are inputting a low-level signal, then the signal will be passed through to the next step without any attenuation. You may often be inputting a signal that has a DC offset, but we want to be able to display that signal in the center of the screen at 0 V. In order to make that happen, there is an internal DC offset of the opposite polarity that is added to the signal to shift the scale. This way it will display on the center of the screen. Lastly, the signal travels into the variable gain amplifier. This type of amplifier will either increase or decrease the gain of your signal dependent on what your V/div setting. So, this again depends on whether you are looking at a low or high level signal. If you are working with a low level signal, you are likely at a low V/div setting which would tell the amplifier the gain should be increased so that we are utilizing the full range of the ADC. If you are working with a high level signal, then the signal would have been attenuated back in the first stage of this process, and the amplifier may then further attenuate the signal in this stage by decreasing the gain, again to scale the signal within the dynamic range of the ADC.
Now that the signal is conditioned to be within the dynamic range of the ADC, it can enter the center of the scope and the analog to digital conversion can begin. The ADC block is the core component of all DSOs. This is where the analog input signal gets converted into a series of digital words. Most of today’s DSOs utilize 8-bit ADCs which will provide 256 unique digital output levels/codes. These digital binary codes are stored in the scope’s acquisition memory, which will be discussed later. In order to obtain the highest resolution and accurate measurements, the scope will try to use the full dynamic range of the ADC. While the signal is being converted in the ADC, the scope is also processing the trigger conditions needed to establish a unique point in time on the input signal upon which to establish a synchronized acquisition. Depending on what you set the trigger acquisition settings to on the scope, the trigger comparator block will output a non-inverted waveform with a duty cycle that is dependent on what you set the trigger level to. Then, depending on what you set the trigger type to (rising edge, falling edge, etc.) the trigger logic block will either invert the waveform before allowing it to pass through, or it will allow the non-inverted waveform to be passed through to the next step. This trigger signal is then used in the timebase block in the next step as the unique synchronization point in time.
The timebase block controls when ADC sampling is started and stopped relative to the trigger event that was just determined in the previous step. In addition, the timebase block controls the ADCs sample rate based on the scope’s available acquisition memory depth and the timebase setting. When the Run key is pressed, the timebase block enables continuous storing of the digitized data into the scope’s “circular” acquisition memory at the appropriate sample rate. While the timebase block increments addressing of the circular acquisition memory buffer after each sample, it also counts the number of samples taken up to a certain number which is dependent on the memory depth of the scope along with the trigger position. Once the timebase block determines that the minimum required number of samples of your signal have been collected, the timebase block enables triggering and begins to look for the first qualifying point of the output trigger comparator. Once the trigger event is detected, the timebase block then begins collecting the required number of samples. Once all of the samples have been stored, the timebase block disables the sampling and the process is pushed on to the next step.
Your signal has now reached the final stage in its journey. Once the acquisition of all of the samples has been completed, the data in the acquisition memory is “backed out” in a last-in-first-out sequence. The signal is reconstructed from the samples and the data is put into the scope’s pixel display memory and it is ultimately displayed on the screen. Once all of the data has been “backed out” of the acquisition memory, the DSP block signals the timebase block that it can begin another acquisition. This is a technique that is unique to Keysight’s custom ASIC technology. Traditionally, most other DSO oscilloscopes would not include this DSP block, but would instead use the scope’s CPU system. That method greatly decreases the efficiency of the scope and slows down the waveform update rate, so you would lose accuracy in your measurements and miss important glitches. Using the DSP block allows Keysight scopes to always operate at high efficiency and display a waveform that is more true to what is actually coming out of your device.
You can see the signal goes through quite the lengthy journey before it is displayed on the scope’s screen, but this all happens in the blink of an eye. To learn more about the fundamentals of oscilloscopes, download Keysight’s application note, Evaluating Oscilloscope Fundamentals.