Paul Capozzoli

PCIe 4.0 is NOT simply an extension of PCIe 3.0

Blog Post created by Paul Capozzoli Employee on Feb 8, 2017

The New Design and Test Challenges

If you plan on leveraging the work you previously did in your PCIe 3.0 design, you are mistaken. A doubling of the speed from 8 gigatransfers/second to 16 gigatransfers/second has a tremendous impact on both the design and validation of your high speed interconnect technology.

 

What are the Key Drivers for PCIe 4.0?

Big Data Needs Throughput. Big data is a term for data sets that are so large or complex that traditional data processing applications are inadequate to deal with them. Challenges include analysis, capture, data curation, search, sharing, storage, transfer, visualization, querying, and updating.

Networking Connectivity Applications.   Streaming movies, streaming sporting events, on-demand TV and the multitude of personal videos uploaded and downloaded is growing exponentially. Simply put, PCIe 3.0 cannot keep up with the latest Ethernet specs without increasing the number of lanes that are required. An increase in the number of lanes means increased cost in terms of power, circuit board layout and required components.  

Storage Technology. PCIe 3.0 has been pushed to its limits for SSD (Solid State) storage devices.   Greater interconnect speeds are required to take advantage of latest storage technologies.

 

Challenges

Channel Attenuation – Higher frequency means greater channel loss. PCIe 3.0 circuit traces can be made to run up to 16-20 inches if design care is taken. PCIe 4.0, on the other hand, is expected to have a maximum trace length of 10-12 inches. It’s simply impossible to use low-cost FR-4, pass through two connectors, and retain enough signal integrity at these speeds; no matter how robust the transmit and receive equalization schemes at the source and endpoint devices are.

So how do you mitigate the effects of greater channel attenuation?    

The answer is retimer(s). A retimer is actually an extension component or, thought of another way, a smart repeater operating at the physical layer to fine tune the signal. So to achieve 20 inches you can place the retimer at 10 inches from both the transmitter and receiver to ensure the required channel length. The link initialization protocol still negotiates the amount of transmitter de-emphasis (to optimize the receiver equalization), but now this negotiation is done to and from the retimer instead of the transmitter.   Therefore, the Retimer, from a link equalization standpoint, behaves exactly like any endpoint or root complex device. It has an upstream and downstream side so when you boot up it starts the initialization. This essentially doubles the essentially doubling the channel length, but at an added cost.  

Signal Integrity – If you are driving a signal into the channel transmit lane (Tx) and it encounters a change in the impedance profile, it will generate a reflection and, if the return loss of the SERDES is sufficiently high, (meaning poor) it bounces back down the channel. If I have high return loss, then the reflected signal may significantly impact the integrity of the transmitted signal.

So whatever design you use for PCIe 3.0 will not work for 4.0. It is not simply a matter of doubling the data rate, because you now have to meet a more stringent return loss characteristic.   So, you actually have to change the design at the silicon level to effectively give you more return loss at the higher frequencies.

Receiver Calibration – The key challenge is the ever shrinking eye height specification. PCIe 4.0 specifies a minimum eye height of 15 mV after equalization with a maximum bit error rate 1 X 10-12.   You are totally dependent upon your receiver’s ability to maximize the eye height. You now have to calibrate to an even finer grain of detail.

 

How do you effectively validate and test?

Keysight is the first to market with full support of both PCIe 4.0 TX Tests under the 0.7 version of the specification and includes the extensive reference clock phase jitter tests required under this specification.

The N5393F compliance test software for transmitter testing of PCI Express 4.0 devices allows for BASE spec testing of new PCI Express silicon under the 0.7 version of the PCIe 4.0 specification. The N5393F product supports transmitter testing of speeds up to 16 GBits/s while also supporting intermediate speeds of 2.5G, 5G, and 8GBit/s. In addition, legacy PCI Express 1.1, 2.X, and 3.X transmitter tests are also supported. This software will run on real time oscilloscopes having 12 GHz (or greater bandwidth) including the Z-Series, V-Series, X-Series, Q-Series, and 90000A platforms.

The N5393F also includes reference clock tests defined in the PCIe 4.0 specification, covering phase jitter requirements. Since the vast majority of PCI Express implementations utilize a common reference clock architecture, it is critical to ensure that a candidate reference clock device meets the many different permutations of phase jitter required for each of the 4 data rates. For PCIe 4.0, this represents over 144 different tests that have to be performed on the reference clock.

The N5393F also adds support for transmitter testing over the new U.2 (or SFF-8639) connector. As PCI Express expands its application base to support Solid State Storage Drives (or SSDs), the U.2 connector has been chosen as the main interface used in computer server platforms.

 Keysight PCIe Compliance Application

Easily select any PCIe transmit compliance application.

PCIe Compliance Application Menu

All testing is automated and produces a hyperlinked HTML report file that makes it easy to identify and study any failed or marginal clock jitter parameters.

Learn more about all of Keysight's PCI Express (PCIe) design and test solutions

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