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2016

What is USB Type-C?

USB Type-C is a USB specification for a small 24-pin reversible-plug connector for USB devices and USB cabling.  It supports 10 Gbps data rates, with a path to 40 Gbps, and can source or sink up to 100 Watts (5 Amps at 20 Volts).  In ALT mode it supports DisplayPort, HDMI, MHL, Thunderbolt, and it is possible to support other serial protocols like Ethernet and even PCI Express.

 

The USB Type-C connectors connect to both hosts and devices, replacing USB Type-B and USB Type-A connectors and cables.  And for the first time, both the connector and the cable direction is reversible! The new form factor is much smaller, essentially the size of a micro USB Type B connector. 

 

Simplicity and capability for the consumer; one connector for a number of applications and uses, its high data rates, power management capabilities, its ease of use and small size are driving this to be THE interface for laptops, tablets, desktop PC’s, phones, displays, cameras, storage devices, automobiles, external batteries, music jacks, USB hubs, TV’s, and the list goes on. Think about it, use your phone to drive a room projector and while you are presenting the projector is charging your phone.  Only with Type-C is this possible.

 

But this capability and versatility creates complexity for designers, integrators and validators.  USB Type-C is one of the more challenging architectures for digital design engineers due to the extreme rise time of the digital signals it’s meant to carry. This, combined with the small physical size of this high-density reversible connector and much higher power specifications increases the risk that design engineers will encounter unforeseen interoperability issues at the fundamental, physical layer. These issues can be avoided by leveraging measurement tools to adequately debug and characterize the performance and validate designs with industry standard compliance applications. 

 

To learn more about USB Type-C, including insights from one of the industry experts, check out our recent Podcast USB Type-C - EEs Talk Tech #1

 

Diagram courtesy USB-IF

 

USB Type-C Design

The USB Type-C connector is small, measuring 8.4 mm x 2.6 mm.  There are four differential data lanes on this interface, two pair of Transmit and Receive.  They are specified up to a maximum of 20 gigabits per second performance.  So, this connector is really able to meet most current needs for data throughput with room to grow as data demand continues to rise in the future.

 

There are four pins on this interface for USB2, shown in grey below, but only two of these pins go through the Type-C cable.  The pins were duplicated to simplify the issue of orientation independence.

 

There are two pins for sideband use which are utilized for the alternate standards, they're called SBU1 and SBU2.  These alternative modes include DisplayPort, Thunderbolt, and MHL.

 

Then there are two pins for configuration and the power delivery channel.  These are the CC1 and CC2 shown in purple in the graphic below.  This is a single communication channel where all protocol and power is negotiated to create a contract between the host and device.  The CC pins have three functions; termination/orientation detection, Vconn Supply, and Power Delivery Channel.  The Vconn wire (one of the CC channels) is used to power active or electronically marked cables.  When a connection is made the host initiates communication on the CC lines and provides a list of its capabilities such as power levels, display modes, maximum data rate, thunderbolt, etc. The device then indicates its capabilities and the two end points agree on a contract.   

 

Finally, we have four pins for Power called the VBus and four pins for ground, and they're located on the diagram below in red and black.  Since there are four of each, this increases the power levels allowed fourfold.  This interface allows for VBus up to 20 volts and current levels all the way up to five amps. That means this interface can carry 100 watts of power! This alone is a major concern as many devices will be fried if the power negotiations are not done correctly and accurately.

Type-C Connector Summary

 

Type-C Connector Summary:

RX/TX Lanes:  4 High-speed differential data lanes, each specified up to 20 Gbps

CC Lines:  Configuration Channel and Vconn Supply

Vbus and GND:  The Power Pins. There are 4 Grounds and 4 Supply Pins that handle up to 20 volts and a maximum of 5 amps.

SBU Lines:  Sideband Use Pins are extra lines for alternative use.

 D+/- Lines:  USB2.0 operation and link communication

 

USB Test Implications

 

Since D+ and D- are USB2, they are assumed to be active in a Type-C design.  Therefore, a full regiment of USB2 test and validation of the device is required in addition to testing Type-C USB3.1.  USB2 runs at 480 Mbps in a half-duplex mode where both protocol and PHY level testing is required.

 

The configuration pins – CC1 and CC2 have a number of different functions. First, they can determine whether a device is connected.  They can also determine connector orientation thanks to a termination aspect related to the CC pin.  The power delivery channel can be configured with these pins to ensure compatibility between the two devices.  Since there are two of these CC pins and only one is connected through to the link, the other may be used to supply power to the cable (Vconn), should it need it.  

 

So what are the test implications for the CC pins?   First, there's power delivery channel testing, which means you need to be able to monitor the data coming through that CC pin. You also may need to test with Vconn loaded or unloaded.  Because your device may need to power the cable, you must be able to terminate the device you're going to test.  In addition, there are serious implications if your power exceeds the proper levels.  An incorrect power level could destroy a device, or it could become a safety issue with life threating consequences.  Either way, extensive testing and validation is mandatory.  The key test requirements for you to consider include protocol and PHY testing for a wide range of voltages and currents as both the provider and the consumer of the power.

 

In the case of USB3 testing, you must test both TX1 and TX2 ports, which will require doubling the test time. You can either do this testing either by taking out the connector and flipping it over and sticking it back in, or you can do an electronic flip.  And if you’re testing Thunderbolt 3 over Type-C you will need to know that all four lanes can be TX or RX.

 

There are even narrower margins when dealing with 10 or 20 gigabits per second data since the eye height and width are decreased significantly.  Since you are concerned about losses in the path, you must ensure you do not have to much loss in the path to your measurement equipment. 

 

Finally, there is testing Type-C alternative modes.  You will need to control the CC line to get into the required alternate mode.  Testing the configuration channel is very important, not only do you need to verify it, but you also have to use it to control states of your device.

 

Type-C incorporates many protocols, very high data rates, power delivery, and of course USB2, and the number of signal to observe and control present a number of challenges for testing.  The good news is that Keysight’s oscilloscopes can help you test and validate your Type-C device with our full range of protocol and physical layer test and compliance applications.

 

Keysight’s Type-C test and validation solutions with oscilloscopes:

 

USB 3.1 Compliance Application – for Gen 1 (5 Gbps) and Gen 2 (10 Gbps)

Keysight’s U7243B USB 3.1 validation and compliance test software provides a fast and easy way to verify and debug your USB 3.1 products.  This software allows you to automatically execute USB 3.1 electrical tests and then displays the results in a flexible report. In addition to the measurement data, the report provides a margin analysis that shows how closely your device passed or failed each test to help you determine the exact signal levels within your design.

 

USB 3.1 compliance test application from Keysight Technologies

USB 3.1 Compliance

 

USB 3.1 Protocol Trigger and Decode

Keysight’s N8821A USB 3.1 Gen1/Gen2 protocol trigger and decode application includes a suite of configurable protocol-level searches and software-based triggering specific to USB 3.1. The multi-tab protocol viewer shows you the correlation between the waveforms and the selected packet using a time-correlated tracking marker so you can quickly move between the type-c physical and protocol layer information.

USB 3.1 protocol decode with time-correlation from Keysight Technologies

USB 3.1 protocol decode with precise time-correlation between waveforms and listing

 

USB PD Protocol Compliance Software

Keysight’s N8840A USB power delivery (PD) electrical and protocol compliance test software helps you quickly validate and debug your USB power delivery provider, consumer, dual-role device, and eMarker cable. USB power delivery compliance test software allows you to automatically execute a USB Type-C power delivery compliance test plan and then see the results in a comprehensive report (.pdf, .csv, and .xml).  These tests conform to the latest USB-IF USB PD specification and test plan and perform electrical physical layer BMC-PHY tests, protocol layer BMC-PROT tests, and power state BMC-POW tests. 

 

USB PD Compliance from Keysight Technologies

USB PD Compliance

 

USB PD Triggering and Decode

You can extend your oscilloscope’s capability with the N8837A USB-PD protocol triggering and decode application which makes it easy to debug and test designs that include USB-PD protocols using a Keysight Infiniium oscilloscope. This application can set up your USB-PD protocol decode in less than 30 seconds and access a rich set of integrated protocol-level triggers. You can save time and eliminate errors by viewing time-correlated packets at the protocol level and quickly troubleshoot serial protocol problems by identifying their timing or signal integrity root cause.

USB-PD protocol decode with time-correlation from Keysight Technologies

USB-PD protocol decode with precise time-correlation between waveforms and listing

 

In summary, it is critical to validate your design to industry specifications to ensure safety as well as device interoperability for new Type-C designs.  Keysight’s oscilloscopes can help you achieve your testing goals and help to get your product to market faster.

Check Back Daily for Scope Giveaways and Special Offers!

It’s November, and many of you know what that means – we are getting close to the largest online shopping day of the year, Cyber Monday. But what would be better than Cyber Monday?  We didn’t want to limit great offers to just one day, so we have been hard at work developing Keysight’s Cyber Week! It’s an entire week devoted to oscilloscope giveaways and special offers.   

 

Keysight’s Cyber Week will run the week of November 28th and will feature a new oscilloscope giveaway and special offer each day, Monday through Friday! If you have been itching for a Keysight oscilloscope or just want to join the fun, check back each day during the week to register for the giveaway, watch the video drawing of the winner, and see the new daily special offer.  You can stay up-to-date on Keysight’s Cyber Week and register for the giveaway by going to www.keysight.com/find/cyberweek. Also, notice that you get an extra entry into the giveaway by telling a friend about it or sharing it on social media (using the ‘Tell a Friend” button on the site). Tune in each day for the live streams of the giveaways drawings!

 

And to stay up-to-date on Keysight oscilloscopes and future events, like our Facebook page and subscribe to our YouTube channel.

 

The team is already prepping for Scope Month 2017! We will be sharing more in the months to come …

In today’s world, it is hard to buy a really bad oscilloscope. But how do you choose the very best oscilloscope, especially when messaging and datasheet specs look so similar between different vendors? I’m here to give you an insider view on the differences between the Keysight S-Series oscilloscopes and the Rohde & Schwarz RTO2000 oscilloscopes. 

 

The Keysight S-Series are digital oscilloscopes with models from 500 MHz to 8 GHz bandwidth. The Rohde & Schwarz RTO2000s are digital oscilloscopes with models from 600 MHz to 4 GHz bandwidth. Both oscilloscopes claim to provide incredible signal integrity.  

 

S-Series oscilloscope materials position this scope as “the new standard for superior measurements” and offering “the industry’s best signal integrity” referencing its incredible 10-bit ADC.  Meanwhile, the RTO2000 materials talk about “excellent signal fidelity” with “up to 16-bit resolution.”  So the question becomes, which of these oscilloscopes truly offers the best signal integrity?

 

First, let’s look at what the Keysight S-Series oscilloscopes offer.

 

The S-Series oscilloscopes contain an incredible amount of innovation, including hardware, software, and the GUI. For hardware innovation, Keysight designed their very own 10-bit ADC to ensure the oscilloscope could offer 10 bits at up to 8 GHz of bandwidth. This custom-designed ADC gives the S-Series oscilloscopes a system ENOB (effective number of bits) of up to 8.1 bits. Additionally, Keysight designed correction filters to run constantly within the FPGA so that magnitude and phase are continuously and properly corrected. This ensures peak-to-peak voltages and rise-times of the measured signal are accurate and consistently displayed.  Plus, the front end was designed for ultra-low noise so that all the benefits of these internal custom components are realized in the measurements.  These oscilloscopes are designed from start to finish to measure and display the signal on your test board, not any unnecessary noise introduced by the measurement system. 

 

This oscilloscope was a revolutionary introduction to the oscilloscope world bringing to market cutting edge, exclusive technology to make cleaner measurements than ever before.

 

Now, I can’t say what went into designing the Rohde & Schwarz RTO2000, but what I can do is make measurements and observe the performance of the final product. So let’s look at how the S-Series and RTO2000 performance compare.

 

For starters, the RTO2000 only has an 8-bit ADCThe S-Series’ 10-bit ADC offers 4X more resolution.  While R&S provides an ENOB specification for their ADC (>7 bits), they don’t publish their system ENOB.  So we should ask, “Why don’t they publish the system ENOB? Isn’t that what really matters when it comes to my measurements?”

 

Your measurements are only as good as the weakest link of your measurement system. So does it matter what the ADC ENOB is if the rest of the oscilloscope design reduces the effective number of bits of the system, as it inevitably will?  In the S-Series oscilloscopes the ADC has 8.7 ENOB, but the important specification is that the S-Series system ENOB is up to 8.1.  

 

To be completely transparent, here is the system ENOB for each model of the S-Series:

Keysight S-Series oscilloscopes ENOB plots

 

The ENOB on the 4 GHz RTO2000 sits right below 6 bits for the entire frequency sweep from 0 – 4 GHz.  The S-Series stays right around 7 ENOB for the frequency sweep from 0 – 4 GHz.   The S-Series has at least one more effective bit across the entire bandwidth of the oscilloscopes. This means that the S-Series has ½ the noise & distortion of the RTO2000.

 

“But what about the 16 bits that were advertised on the RTO2000?” you may ask. This is available with the RTO2000 16-bit high definition mode, option RTO-K17.  First, I suggest you get a quote for how much this option will cost in addition to the cost of the oscilloscope.  It may be upwards of $3,000 USD since the same option on their lower performance RTE digital oscilloscopes (200 MHz to 2 GHz), is priced at $3,175 USD. 

 

And here is what the RTO high definition option provides compared to the free S-Series high resolution mode:

 

Bandwidth

RTO2000 High Def Mode

S-Series High Res Mode

10 kHz – 50 MHz

16 bit

13 bit

100 MHz

14 bit

13 bit

200 MHz

13 bit

13 bit

300 MHz

12 bit

13 bit

500 MHz

12 bit

12 bit

1 GHz

10 bit

11 bit

 

 

You can see that this expensive upgrade only provides more bits than the S-Series from 10 kHz – 100 MHz. And in the plot above, you can see that it only gives you lower noise on the RTO than the S-Series in the same limited bandwidth. In all comparable high resolution modes of operation, the S-Series has lower noise. So, is it worth it to pay extra for the RTO high definition option?

 

Now let’s look at how the noise of the oscilloscopes compare, without the high resolution options turned on.  Below is a graph that shows the noise of both oscilloscopes as the vertical scale (volts on screen) is changed.

 

 

Keysight S-series clearly has much lower noise at all settings than the R&S RTO2000, meaning the signal you measure with the S-Series is much more similar to the signal on your DUT than what the RTO2000 would display.

 

Looking at the test results, my conclusion is the following: the Keysight S-Series has higher ENOB and are much lower noise oscilloscopes than the RTO2000 scopes.  The RTO2000’s signal integrity message does not hold up under testing. If you’re looking for a low noise scope with superior signal integrity, the S-Series oscilloscope is the best scope for you.

 

Coming soon will be Part 2 of the S-Series vs RTO2000 which will look at more features of the oscilloscopes, including other key specs, the GUI, probes, and applications. 

 

 

Specifications pulled from “R&S RTO Digital Oscilloscope Specifications” data sheet version 04.00, June 2016.

Measurements were made on an S804A with firmware version 5.70 and an RTO2044 with firmware version 3.30.1.1

R&S messaging pulled from R&S RTO2000 product page,  Nov. 3, 2016: https://www.rohde-schwarz.com/us/product/rto-productstartpage_63493-10790.html

Introduction

In a previous post we described how phase noise information can be extracted from real-time oscilloscope waveform acquisitions using two different techniques to demodulate the phase. In this article we’ll take a look at the potential accuracy of the serial data clock recovery technique, what kinds of signals can reasonably be analyzed, and some ways to improve such measurements.

 

Accuracy

In order to check that the oscilloscope phase noise measurement is accurate we can use a clean signal source with a broadband random phase modulation source built-in. By injecting a relatively large PM amplitude over broad frequency we can verify the noise level by comparison with a measurement made on a Signal Source Analyzer such as the Keysight E5052B.

 

In the measurement below (Fig. 1), the SSA result is in blue and the oscilloscope measurement (using a Keysight MSOS804A) result is in green. There is excellent agreement over the range of injected PM. Above 2 MHz the SSA’s lower noise floor is the reason for the separation in the curves.

Fig 1

 

Measurement Noise Floor

The measurement floor of a jitter measurement on a real-time sampling oscilloscope is affected by both vertical (voltage) accuracy and timing accuracy. Vertical noise in the sampling system, stability of the timebase, the phase noise of the oscilloscope’s own oscillator & imperfections in the interleaving architecture of the scope will all contribute to errors in the jitter measurements and thus the measured phase noise.

 

An example of an oscilloscope jitter measurement floor specification is:

oscilloscope jitter measurement floor specification

The Intrinsic Jitter portion is dependent on the stability of the internal timebase reference. For the highest performance scopes such as the 63 GHz Keysight Z-Series this can be as low as 50 fs but it must be noted that this value is often only valid for fairly short acquisition times. To measure close-in phase noise we need to capture long acquisition times and the intrinsic jitter of the oscilloscope will increase due to its own phase noise.

 

Noise Floor & Signal Slew Rate

In most cases the first term in the equation dominates the jitter measurement floor. Both signal and oscilloscope vertical noise combine with the finite slew rate of the signal to create apparent horizontal displacement of edges, i.e.: jitter. Thus it is crucial to choose an oscilloscope with as low a vertical noise bandwidth density as possible. A further improvement in jitter measurement floor can be achieved if the oscilloscope also has the ability to limit the bandwidth to an arbitrary frequency. Since the phase noise information is contained within a bandwidth 2*fc we can drastically limit the measurement noise in many cases.

 

Below (Fig. 2) is a set of phase noise measurements made using a Keysight 8 GHz S-Series oscilloscope. The signal source was a 100 MHz sine wave from an ultra-low phase noise Performance Signal Generator, E8267D. The true phase noise of the E8267D (as verified with an SSA or other suitably low phase noise instrument) is well below the oscilloscope measurements so this enables us to see the measurement floor of the scope.

 

The oscilloscope bandwidth was adjusted for each measurement as follows:

 

Blue = 8 GHz, Green = 4 GHz, Red = 1 GHz, Cyan = 200 MHz.

Fig. 2

 

The phase noise floor at 1-10 MHz offsets drops from ~-124 dBc/Hz to -140 dBc/Hz when going from bandwidth of 8 GHz to 200 MHz. This can be explained by the fact that we’re reducing the bandwidth by a factor of 200 MHz / 8 GHz. If the noise of the oscilloscope is fairly flat with bandwidth we should expect a drop of about 10*log10(0.2/8) = -16 dB. This is not the case at all frequencies. At low frequencies the phase noise of the oscilloscope’s internal reference starts to dominate. At higher frequencies we see the limit of the ability to produce a perfect brick-wall bandwidth limit filter at 200 MHz. This means we are still getting some scope noise beyond 200 MHz included in our measurement.

 

The benefit gained in limiting the scope’s bandwidth is highly dependent on the slew rate of the signal to be measured and the ratio of the signal frequency to the full scope bandwidth.

 

Noise Floor & Scope Internal PLL/Oscillator

It is often the case with phase noise measurements that low frequency phase modulation is of particular interest. In addition to requiring responsive, deep memory acquisition as discussed in a previous article it is also important to have an oscilloscope with an extremely stable timebase and well-designed PLL circuitry as this will dominate the low frequency measurements.

 

In the measurement below (Fig. 3) you can see that an older technology oscilloscope (green) has higher phase noise at close-in offsets than the newer technology oscilloscope (blue).

 

Fig. 3

 

Further improvement of the close-in phase noise might be possible using an external reference clock to the oscilloscope which is cleaner than the internal oscillator. Below (Fig. 4) is a comparison measurement of a Keysight V-Series phase noise floor using the internal oscillator (blue) versus a Wenzel 10 MHz reference (red):

Fig. 4

 

Noise Floor & Sample Rate

Previously I mentioned that the oscilloscope sample rate must be kept high in order to accurately place the edges. It would be nice to be able to reduce the sample rate as it would allow us to use less acquisition points and thus either make faster measurements, increase averaging or go to lower frequency offsets. But we must be careful to make sure the sample rate does not impact our measurement accuracy significantly.

 

Below (Fig. 5) we can see the impact of reducing the sample rate (bandwidth is maintained at 200 MHz for all measurements) on the phase noise measurement of the same, clean 100 MHz sine wave.

 

Blue = 1 GSa/s, Green = 5 GSa/s, Red = 10 GSa/s, Cyan = 20 GSa/s.

Fig 5

 

You can see that eventually reducing the sample rate does impact the phase noise measurement floor. In this case there is not a significant difference between using 20 GSa/s and 10 GSa/s, but below that sample rate there is an increase in the results. The extent of the impact will also depend on the shape & slew rate of the signal edges.

 

Phase Noise of a Data Signal

Since the oscilloscope uses a clock recovery algorithm to extract the TIE information, an advantage of this approach is the ability to measure the phase noise of data signals. In the example below (Fig. 6) the phase noise of a high speed pattern generator is measured. The only difference in the measurements is the pattern used. Blue is a pseudo-random bit sequence and green is a repeating one-zero clock pattern:

Fig. 6

 

There is some difference in phase noise at high frequency offsets due to the nature of the generator.

 

Summary

To summarize, real-time sampling oscilloscopes – although perhaps not a first choice for phase noise measurements – can be an acceptable choice depending on the measurement requirements. For close-in phase noise measurements (typically less than 1 kHz or so) a dedicated phase noise analyzer or spectrum analyzer will provide a faster, more accurate measurement. However for measuring relatively low cost oscillators and PLL circuits or for wide bandwidth requirements an oscilloscope with a clean timebase and low noise front end may be very capable of making the required measurement. In addition using a real-time oscilloscope has the advantage of allowing you to extract phase noise from a serial data signal if a serial data clock recovery approach is used.

 

Questions? Visit the Infiniium phase noise forum.

What is Phase Noise?

Wikipedia defines phase noise as, “the frequency domain representation of rapid, short-term, random fluctuations in the phase of a waveform, caused by time domain instabilities (jitter)”. The inclusion of the word noise in the name tells us that this does not refer to any spurious or deterministic terms. The mention of “short-term” in the definition is meant to distinguish from other ways to determine the cleanliness of a clock source such as stability in points per million, ppm. This is usually measured over a much longer timescale such as seconds or minutes.

 

Phase Noise information is usually presented in a log frequency plot such as the one shown below (Fig 1) where the amplitude units are dBc/Hz (decibels relative to the carrier power normalized to a 1Hz bandwidth). The x-axis is the frequency offset from the nominal signal or “carrier” frequency.

Fig. 1

 

For a more complete explanation of what phase noise is I recommend the application note, “Using Clock Jitter Analysis to Reduce BER in Serial Data Applications.”

 

Why use an Oscilloscope?

Before describing how to measure phase noise using an oscilloscope it would probably be a good idea to ask “why use a real time scope for this kind of measurement?” There are instruments dedicated to the measurement of phase noise such as the Keysight E5052B Signal Source Analyzer which have a much lower phase noise measurement floor than any oscilloscope. An SSA is also able to accurately measure much closer-in phase noise offsets and much quicker than any oscilloscope. However there are typically some measurement restrictions such as limits on the maximum frequency offset range available. 100 MHz is a typical maximum offset for a phase noise analyzer. For clock frequencies greater than 100 MHz it may be desirable to measure out to higher frequency offsets than can be measured with these tools. Also an oscilloscope can measure the phase noise transferred onto a data signal, not just on a clock.

An oscilloscope may also simply be good enough for the measurement requirements if your budget doesn’t allow for a dedicated instrument for measuring phase noise.

 

Extracting the Phase

An oscilloscope captures and digitizes the complete signal waveform and there is more than one way to extract the phase noise information from the digitized waveform. In this article we will briefly describe two methods:

  1. Clock Recovery
  2. Phase Demodulation using Vector Signal Analysis

 

Phase Demodulation via Serial Data Clock Recovery

Oscilloscopes measure timing variations (jitter) of a serial data or clock signal by analyzing where a signal crosses a voltage threshold and comparing that to the edges of some reference clock. In the case of phase noise we want the reference clock to be an ideal, constant frequency clock. Most modern oscilloscopes have clock recovery algorithms to extract a clock from the signal. In many cases it is desirable that the algorithm emulates a Phase Locked Loop (PLL) but in our case we simply want to extract a constant period ideal clock so that we do not “track out” any of the phase variations like a PLL would. An example of the setup of clock recovery is shown below. (Fig 2) The algorithm can be set to adjust to the nominal signal frequency and phase based on each captured acquisition.

Fig 2

 

A time interval error (TIE) measurement on an oscilloscope will produce a time series of the absolute time error of each edge relative to the ideal clock. To convert to phase (radians) error we simply multiply by 2*pi*fc where fc is the clock carrier frequency.

φ[rad]=2*π*TIE(t)*fc

 

A Time Interval Error trend can be transformed to frequency space with an FFT to give something called a Jitter Spectrum. Most modern oscilloscopes have this capability built in or as an option (Fig 3).

 

Fig 3

 

Averaging of the jitter power spectrum over multiple acquisitions is necessary to get a clean view of the measured phase spectral density.

 

The Jitter Spectrum approach yields a maximum frequency offset (fφ_max) equal to the carrier frequency itself (when both rising and falling edges are included in the TIE).

 

The minimum frequency offset (fφ_min) is principally bounded by the length of time of the TIE capture. I.e.: no frequency content is captured lower than the inverse of the time between the first edge in the TIE trend and the last.

minimum frequency offset is bounded by the length of time of the TIE capture

Herein lies the difficulty with measuring phase noise on a real-time sampling oscilloscope. A high enough sampling rate must be maintained to accurately capture the edges in time, but in order to also get the low frequency content very large acquisition memory depths must be used to capture more time.

 

Example:

SaRate = 80 GSa/s

fφ_min = 100 Hz

Required Memory Depth = 800 Mpts

 

Each acquisition must then be processed to find the edges using clock recovery, Fourier transformed to create the jitter spectrum and then multiple acquisitions must be averaged. The oscilloscope must have deep memory available and be able to process it quickly.

 

We now have the fundamental information contained in a phase noise measurement but ideally we’d like to have units of dBc/Hz as is common practice for these measurements. Also most phase noise plots have a log frequency scale to enhance the viewing of close-in phase noise offsets.

 

As an example if we set up the TIE measurement in units of seconds rather than radians then to convert to units of dBc we do the following:

phase noise

 

However note that the phase noise above contains the energy from both sides of the carrier. Most often people think of the Single-Sideband (SSB) phase noise which is defined as the noise on a single side of the carrier spectrum & denoted by the use of the symbol L. Thus we must divide the above phase noise by 2 since L(fj) = 0.5*Sφ(fj) and also divide by the square root of the resolution bandwidth of the jitter spectrum to normalize to a 1Hz bandwidth.

 

Thus:

normalized phase noise calculation

 

An example of such a measurement and conversion is shown below.  (Fig.  4) This is a measurement of a very clean 100 MHz sine wave using a Keysight Infiniium DSAV334A oscilloscope in conjunction with an application called Infiniium Phase Noise. In addition to the averaging of the jitter spectrum, smoothing and spur removal techniques are employed in this application to get a better measure of the random phase noise floor.

 

 

 Fig. 4

 

Phase Demodulation via Vector Signal Analysis

Vector Signal Analysis software such as the Keysight 89600B can use a variety of hardware to acquire data including real-time oscilloscopes. Analog Phase Demodulation algorithms work differently than serial data clock recovery but with a very similar outcome.

Shown in Fig 5 is a high-level block diagram of how the phase demodulation is performed in the 89600B VSA software. An ideal local oscillator (LO) is mixed mathematically with 2 copies of the digitized signal – one of which is 90 degrees out of phase with the other. The resultant signals are then low-pass filtered to remove the high-frequency mixing products and leave just the phase (and frequency) error. This can then be displayed in many formats including the phase spectrum.

Fig 5

 

The VSA PM demodulation algorithm has optional automatic carrier frequency and phase tracking algorithms as shown below (Fig. 6):

 

Fig. 6

 

The auto-carrier frequency algorithm adjusts the clock frequency to the measured nominal signal clock frequency rather than the value input by the user (just like the serial data clock recovery). This frequency is re-calculated for each new waveform acquisition.

The auto-carrier phase algorithm also adjusts to the nominal phase of the incoming signal on each acquisition.

 

 

Below (Fig. 7) is a measurement of the same clean 100 MHz sine wave with the same DSAV334A oscilloscope but using the VSA software to control the scope acquisition, demodulate the phase and average the phase noise spectrum. There is excellent agreement between the two phase demodulation techniques.

Fig. 7

 

Summary

Different algorithms can be applied to digitized waveforms acquired by real-time oscilloscopes in order to recover the phase noise information and thus present phase noise plots. There are tradeoffs between the techniques which are outside the scope of this article but we can conclude that it is both possible and useful to be able to make phase noise measurements with an oscilloscope if the need arises. In part 2 of this article, we will explore tradeoffs and accuracy of using a real-time oscilloscope for these kinds of measurements. 

 

Questions? Visit the Infiniium phase noise forum.