Here in Keysight Oscilloscopeland we talk a lot about our ASICs (application specific integrated circuits). But why? Who cares about the architecture of a cheap oscilloscope? All that matters is how well it works, right? We agree. That’s why we design and use oscilloscope-specific chips for all our scopes.
How, though? Custom ASICs don’t just materialize out of thin air, it takes years of planning and R&D effort. Here’s a high level look at what it takes to make an ASIC.
The making of an ASIC
There are several different steps (and teams) involved in the creation of an ASIC. Before anything is started, there must be a long-term product plan – what do designers want to have 5-10 years down the road? Future products will have new specs or features that will sometimes warrant an ASIC. To make that decision, product planners meet with the ASIC planners.
A custom 8 GHz oscilloscope ADC, used in Keysight S-Series Infiniium oscilloscopes.
First up is the planning team. They ask “what chips do we need to have in a few years? – Let’s make that.” And, “what will be available off-the-shelf in a few years? - Let’s not make that.” The planners will also make cost vs. performance trade-off decisions (device speed, transistor size, power consumption, etc.).
Also, ASICs generally fall into one of two categories: digital or analog. Analog chips are essentially signal conditioning chips designed to massage signals into a more desirable form. Digital chips are essentially streamlined FPGAs, designed for processing data inputs and providing coherent data outputs. For example, our MegaZoom ASICs take data from an oscilloscope’s front end circuitry + ADC and output waveforms, measurements, and other analytics.
Fig 1: The Keysight-custom ADC and processor chips on the InfiniiVision 1000 X-Series oscilloscopes
It's worth noting there's a third type of ASIC - a mixed signal ASIC like an ADC (Fig 1.)
Now, let's take a closer look at process of creating digital ASICs, like the MegaZoom processor in the InfiniiVision oscilloscopes.
Once the chip is well defined by the planning, the front-end team gets to work. They are responsible for the “register-transfer level” (RTL) design (and typically spend their days with Verilog or VHDL). Their goal is to create a functioning digital model of the chip, but not a physical model. The RTL team is ultimately responsible for taking the chip design specs and turning it into actual logic and computation models. To do this, they use digital design components/building blocks and techniques like adders, state machines, pipelining, etc.
The RTL team is ultimately responsible for taking the chip design specs and turning it into actual logic and computation models.
As the front-end team is working, there’s also test team that works to check the RTL for errors bugs. The goal is to try to avoid situations like the infamous Pentium FDIV bug that cost Intel nearly $500 million in 1995.
Once the RTL is proven to be functional by the test team, it is synthesized into a netlist. This essentially means that the RTL is converted from logic blocks into individual logic gates. Today, software handles this, but historically it was done by hand and engineers used truth tables and Karnaugh maps. The netlist is then run through a formal verification tool to make sure it implements the functionality described in the RTL before being passed to the back end team.
Once the logic is verified, it’s time to physically implement the chip. This is typically known as “floorplanning.” Floorplanners use crazy-expensive software (hundreds of $k) to place the RTL onto the chip footprint. In reality, the back end team generally gets early versions of the netlists so they can get a head-start on floorplanning.
The back end work begins with an overall placement of design blocks on the chip. The general workflow for the back-end team is:
- Individual gate placement
- Clock tree building
- Static timing analysis
For the chip to function properly, gates involved in the same computational processes should be close together. Also, designers have to make sure that power can be distributed properly throughout the chip.
A clock tree is a clock distribution network designed to make sure the clock reaches each of the gates at the same time. If clock edges arrived up at different times to different parts of the chip, it could cause painful timing errors. Sometimes, designers also intentionally add some clock skew to keep an edge from arriving too soon.
The back end work begins with an overall placement of design blocks on the chip.
Once placement is complete, software then auto-routes the connections between gates. You’re probably familiar with the phrase “never trust the autorouter.” In this case though, that’s really the only option unless you want to manually route hundreds of thousands (or millions) of connections.
Fig 2: Routing of an oscilloscope acquisition board
Finally, an ongoing concern throughout the whole process is whether or not the design is actually manufacturable. This is known as DRC (design rule checking). Basically, this is a set of rules designers provide to the software to tell it what architectures (aka physical shapes) are and aren’t physically possible. Then, there's a layout vs. schematic check (LVS) to verify that the physical geometries actually implement the desired circuitry.
Once the front end and back end teams are done, it’s party time. This stage, known as “tape out,” is when the final design is prepped for production. Massive files are sent to the fab, who creates photomasks for each layer of the ASIC. It’s not unusual for there to be 30-50 masks for a single chip.
In the final stage, known as “tape out,” the final design is prepped for production.
Once the masks are created, a number of different techniques are used to manufacture the chip. Usually a combination of photolithography, acid baths, ion implantation, furnace annealing (baking), and metallic sputter deposition is used. Each silicon wafer holds dozens (or hundreds) of identical layouts that will later be cut up into discrete chips.
The completed wafer is then tested for manufacturing errors. Depending on the size of the wafer and complexity of the process, planners can usually predict the failure rate of each chip. Microscopic anomalies, like a speck of dust under mask, can cause a chip to fail. “Scan testing” is used to check each gate. Scan testing consists of applying a pre-determined pattern of signals that will test every single gate on the chip, and each chips’ output is compared to the expected output. Each die is tested, and the chips that pass are sent on to be packaged.
Good dies are then placed into packages and tested again. The packaging team typically designs a custom package for the die, and needs to consider signal integrity, cost, thermal regulation, and reliability. Often, we at Keysight will re-design the package of an existing ASIC using updated technology to reduce hardware cost and improve reliability of our oscilloscopes.
The packaging team typically designs a custom package for the die, and needs to consider signal integrity, cost, thermal regulation, and reliability.
For example, the ADC on our inexpensive oscilloscopes is the same ASIC used in some legacy oscilloscopes, but by improving the packaging over time we’ve reduced the package cost by nearly 5x. Thanks to that cost reduction, what was once used for only for a top-of-the-line oscilloscope we can now use in our cheap oscilloscope.
Once a chip is manufactured, tested, and packaged, it still needs to be surrounded with support circuitry. For example, what good is an op amp if you never configure it with resistors? But, that’s a topic for another blog post.
How it’s made
So, while you wouldn’t want to use this description to go design your own ASIC, you should now have a better understanding of what it takes to produce an ASIC. It’s a lot of work, but the benefits they offer compared to FPGAs are often worth the investment. For any given Keysight oscilloscope, we use a few different ASICs. We use analog ASICs for the front end, a custom low-noise ADC, and often a custom processor as the brain of our oscilloscope. While this comes with a fairly large non-recoverable engineering expense (NRE), being able to use the same chip in our $45,000 oscilloscopes and our $450 oscilloscopes earns our oscilloscopes special place on the budget-conscious engineer’s bench.