#DDR #DDR4 #DDR5 #DRAM #RAM
DDR4 was the first DRAM technology to break the High Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This webcast will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.