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PAM-4 Simulation and Design of Next Generation High-Speed Digital Links

Blog Post created by stmichel Employee on Aug 8, 2017

As people use more applications on their phones, tablets, computers, and Internet of Things (IoT) devices, the  network needed to deliver the data is constantly being upgraded for the constantly increasing bandwidth demand. Four-level pulse amplitude modulation (PAM-4) signaling is a leading contender for implementing the 56G lane data rate which will enable 400G links for the next upgrade in network bandwidth.

#PAM-4 is gaining traction for high-speed #SerDes links over an electrical backplane, especially for designs attempting to deliver greater than #56Gbps throughput. Doubling data rates with traditional non-return to zero (NRZ) signaling is technically challenging due to the extremely signal loss at high frequencies. The alternative signaling technique, PAM-4, is used to transmit at 28Gbaud, but with 4 amplitude levels (where each symbol represents 2 bits), effectively delivering 56Gbps throughput.

 

From 10 to 56 G

 

Conventional impairments such as jitter, noise, channel loss, and inter-symbol interference (ISI) have more complicated expression with PAM-4. In addition to this, receiver architectures for PAM-4 introduce new concepts for system designers such as:

  • 3 Slicer outputs with time-varying voltage thresholds (for deciding which amplitude level has been received)
  • Individual Slicer Timing Skew (each Slicer's decision point can be offset in time from the other two)
  • Multi-tap decision feedback equalization (#DFE)
  • #Clock and Data Recovery 

The complex interaction of these new concepts influences specific design trade-offs for PAM-4.

 

Keysight’s Advanced Design System (ADS) offers a design space with a channel simulator, accommodating not only lumped-element models but also the distributed transmission line, S-parameter, and EM models that are essential to model high-speed PCB traces and determine ultralow #BER contours in seconds not days.

 

How to send data at 56 Gbps

The ADS #channel simulation enables a comparison of PAM-4 versus NRZ technology. This example demonstrates the trade-off of price vs performance in #PCB design. Cheaper PCB materials with more loss and no-back-drilling of vias are more likely to exhibit resonances at higher frequencies. This channel may not support NRZ to 56Gbps, but will support PAM-4 more easily, if the resonances are higher in frequency than the main spectral content of the #PAM-4 signal.

 Adaptive DFE

The system designer attempting to compare NRZ to PAM-4 trade-offs needs to use PAM-4 IBIS-AMI models from SerDes vendors within their channel simulation. Keysight Technologies' continuing leadership in the IBIS Open Forum, Keysight EEsof EDA now offers support for the new IBIS v6.1 specification. Developed in collaboration with the industry's leading PAM-4 SerDes IC vendors, the ADS Channel Simulator provides a trusted bit-by-bit simulation engine for PAM-4

 

Join us at ECOC in Gothenburg to experience this solution live

 

Where to find more information:

For more information on PAM-4 solutions from Keysight Technologies, refer to http://www.keysight.com/find/pam4

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