USB 3.1 Testing: Why Adhering to the Spec will cause Failures

Blog Post created by jitlim Employee on Dec 7, 2016

For proper USB testing, the first step is to get a copy of the USB 3.1 spec, CTS (Compliance Test Specification), and ECNs (Engineering Change Notice) from the USB-IF and ensure that your product meets the spec requirements.

The link budgets for USB 3.1 are shown in Figure 1. To understand this diagram, let’s use the last row as an example. A 10G Type-C Host has an IL (Insertion Loss) budget of 8.5dB@5GHz. Similarly the Type-C to Type-C cable budget is 6dB and the 10G Type-C Device has up to 8.5dB of loss budget. Assuming you are a Gen 2 Type-C Host silicon designer, you would need to add 23dB of loss to ensure that your silicon can meet the total link loss budget.

However, the bigger challenge is you cannot control what your customer does with your silicon.

Let’s say your customer also implements your silicon in Row 5. In this case, you would need to add 13dB@2.5GHz of IL to your testing. But what if your customer is implementing your silicon for Row 6? You would need to add 17dB of loss for the same silicon. And for Row 3, for the same silicon, you would need to add 20dB.

Figure 1. USB 3.1 Link Budgets


Things get even more complex if your customer has a Type-C ALT mode implementation shown in Figure 2.

Although your silicon worked great in your customer’s Std A – Std B configuration, Type-C ALT mode potentially adds a switch for USB and DP ALT mode, then another switch for CC1 or CC2. One switch can easily add another dB of loss to your channel budget.


Figure 2. Type-C implementation challenge. (Courtesy USB-IF)

Now, what happens if you are a system integrator designing Hosts and Devices and need to pass Compliance?

Compliance testing looks for a PASS under controlled conditions. However, all your products and test results will generally have a Gaussian distribution. If you rerun the same measurement on a single DUT, or rerun the same measurement on multiple DUTs, you will see this distribution. If the test result variation of your product is too close to the spec, you will see failures.

Finally, you cannot control the final user’s link partners and cable. Your silicon may meet spec, and the system integrator may implement a design that also meets spec. But the final customer might connect a non-compliant cable to the link.

To ensure that ALL of your products work as intended, you must always test your silicon for BEYOND spec and your systems to have margin BEYOND compliance.

Figure 3 shows test results unique to the Gen 2 LTSSM (Link Training Status State Machine). Although it is important that the results show PASS in the first column, it is crucial that the numbers in the 6th column are analyzed to determine design margin.


Figure 3. USB 3.1 Gen 2 10Gbps LTSSM TX Test Results

An additional step, especially if you are a silicon designer, would be to embed additional channel loss beyond the compliance channel. And determine at what point your DUT will fail. If you add sufficient IL, your silicon will fail. You need to where that point is. Oscilloscopes today have SW that seamlessly allow you to embed additional IL and rerun the Base or Compliance tests.

The same approach applies when you perform RX testing. The dark line in Figure 4 is the Compliance requirement for USB 3.1 Gen 2 at 10Gbps. A compliant product would simply be tested and PASSed along the dark line. The “Last Pass/First Fail” points above the Compliance curve is the JTOL (Jitter Tolerance) plot. It determines how much additional SJ (Sinusoidal Jitter) can be added beyond compliance before the DUT fails. Your DUT may pass RX Compliance, but you really need to know when it fails.


Figure 4. USB 3.1 Gen 2 JTOL Plot


For RX testing Beyond Compliance, you can similarly add increasing amounts of RJ, SJ, and IL. The neat thing is modern BERTs can seamlessly allow you to dial in additional RJ, SJ, and ISI with a mouse click.


It is very important that silicon passes the Base Spec and Hosts/Device pass the Compliance Spec. But this approach to “Beyond Spec and Beyond Compliance” testing will lead to better designs, increased silicon yield, higher manufacturing throughput, lower customer returns, and better customer experiences. In a future blog, I will share some of the common pitfalls that prevent DUTs from even PASSing compliance!