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It has been quite a while since our last PAM4 tutorial.

The 400G standards have matured since and on the electrical and optical side as expected pulse amplitude modulation (PAM4) is a predominant modulation format.

The transition from non-return-to-zero (NRZ) to PAM4 means many substantial changes. It comes alongside with new quality tests, test pattern and quality parameters.

In this part of the tutorial series we’ll introduce you to the differences of NRZ and PAM4 optical test parameters. New PAM4 measurements used in multiple IEEE 802.3bs/cd clauses include outer optical modulation amplitude and outer extinction ratio. For PAM4 the eye mask  is  no longer measured.  A new key quality measure is being introduced: transmitter dispersion eye closure (TDECQ). Q stands for 'quatenary'.

While in NRZ the corresponding  transmitter dispersion penalty (TDP) is determined by directly measuring the bit error rate (BER), for TDECQ the symbol error rate (SER) is measured indirectly.

This makes TDECQ cost-effective and relatively fast to measure in comparison to TDP.

 

See in detail how TDECQ is obtained to make statements about the performance of your transmitter and learn about the respective IEEE 802.3bs/cd standard requirements.

Watch tutorial.

 

TDECQ Tutorial

 

 

 

 

 

 

 

One of the most important ways to determine the quality of a digital transmission system is to measure its Bit Error Ratio (BER). The BER is calculated by comparing the transmitted sequence of bits to the received bits and counting the number of errors. The ratio of how many bits received in error over the number of total bits received is the BER. This measured ratio is affected by many factors including: signal to noise, distortion, and jitter.

BER Equation

The most obvious method of measuring BER is to send bits through the system and calculate the BER. Since this is a statistical process, the measured BER only approaches the actual BER as the number of bits tested approaches infinity. Fortunately, for most cases we need only to test if the BER is less than a predefined threshold. The number of bits required to accomplish this will only depend on the required confidence level and BER threshold. The confidence level is the percentage of tests that the system’s true BER is less than the specified BER. Since we cannot measure an infinite number of bits and it is impossible to predict with certainty when errors will occur, the confidence level will never reach 100%.

To calculate the confidence level (CL), we use the equation:

CL Equation

For our purposes, we will only be concerned with the case where there are zero errors detected. To calculate the BER when there are errors detected and for a mathematical explanation of the origins of these equations, see Total Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method. This equation can be rearranged to calculate the number of bits required for a given BER and confidence level (CL).

N490xA Nbits Equation

As an example, if our specified BER is 10-12 and we require a typical confidence level of .95 (95%), the required number of bits to test without any errors is 3x1012. Once we have tested this many bits without error, we can be sure that our actual BER is less than 10-12. Whether the actual BER is 10-12, 10-15 or 3.1x10-14 is unimportant. Again, note that this value is independent of the data rate that the bits are being tested at. To determine the test time required, the number of bits to be tested is simply divided by the bit rate (bits/second). Resulting in the equation:

time equation

At a standard 95% confidence level, we can substitute 0.95 in for CL and obtain a very usable function:

A table of test times at 95% confidence level is given for popular standard bit rates and bit error ratios assuming every single bit/symbol is compared.

 PCI Express 5Gb/s
NRZ
PCI Express 16 Gb/s
NRZ
IEEE 802.3 bj 25.78125 Gb/s
NRZ
IEEE 802.3 bs 26.5625 Gbd
PAM-4
IEEE 802.3 bs 53.125 Gbd
PAM-4
10-15~ 165 hrs~ 51 hrs~ 32 hrs~ 31 hrs~ 16 hrs
10-12~ 10 min~ 3.1 min~ 1.9 min~ 1.9 min~ 1 min
10-9~ 59 secs~ 19 secs~ 12 secs~ 11 secs~ 6 secs
10-6~ 2 µsec~ 0.7 µsec~ 0.4 µsec~ 0.4 µsec~ 0.2 µsec

1. For PAM-4 coded signals, the corresponding symbol error ratio

Table 1. The table shows how long it takes to confirm a target BER with a 95% confidence level for various popular bit rates and interface standards.

For this example, we will simply choose Accumulation end = Full Duration and Accumulation Duration = Fixed Time and set the Accumulation fixed time to 10 seconds.

To measure BER to a given confidence level with J-BERT M8020A or a M8040A high-performance BERT, there are a few things you need to do.

  1. Set up the Error Detector for your configuration. This may include Differential/Normal transmission and/or clock data recovery or line coding.
  2. To start the BER test, open the M8070A system software for BER measurements and select in the menu bar “measurements”.
  3. Set the M8046A under the acquisition parameters, you may choose which

- analyzer hardware to select,
- accumulation end and duration,
- “pass/fail” for a target BER and confidence level,
- “number of bits”, and
- “Full Duration” for selecting a measurement time.

.

Acquisition parameters for the Bit Error Rate (BER) measurement

Figure 1. You can adjust the acquisition parameters for the BER measurement

 

To start and view your results, go to the measurement menu and select “Error Ratio”. Hit the green arrow to start the accumulation the J-BERT M8020A or M8040A will perform the test for 10 seconds. . As you can see in Figure 2, we injected a BER of 10-6 four times button. Now you may view the results. In this example, we measured a data rate of 5 Gb/s for 10 seconds, resulting in a bit count of 50.1 M bits. We measured an Error Count of 4020 bits, resulting in an Error Ratio (BER) of 8.02 * 10-8. According to our calculations above in Table 1, we would need to measure zero errors for ~1 minute at this data rate to ensure a BER of less than 10-11.

 

Error ratio result display in M8070A

Figure 2: Error ratio result display in M8070A

M8040A 64 Gbaud high-performance BERT (Bit Error Ratio Tester)

Figure 3: Keysight M8040A 64 Gbaud high-performance BERT (Bit Error Ratio Tester) for simplified and accurate test of 400 GbE PAM-4 & NRZ devices.

 

BERT M8020A high-performance BERT (Bit Error Ratio Tester)

Figure 4: Keysight J-BERT M8020A high-performance BERT (Bit Error Ratio Tester) for accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s. 

What to expect from PCIe Gen5?

Ever heard of Cache coherent interconnect for accelerators (CCIX), GenZ, NVLink or OpenCAPI? If you haven’t, you soon will. These wave of technologies is currently pushing the incumbent PCIe to faster speeds. PCIe Gen4 is just becoming mainstream, but has limited bandwidth, given the needs of today’s technologies at only 16 Gbps. This is a far cry from today’s IEEE-led interconnect technologies that are now looking to data rates well above 100 Gbps. As a result, new technologies have appeared to speed up the interconnect space. These buses look to specialize in areas where PCIe is not as customized. For example, GenZ is targeting memory-to-CPU connections and moving to speeds above 30 Gbps. Another technology, NVLink is being developed to connect GPUs to GPUs. CCIX looks to replace PCIe at 25 Gbps.

This is where this whole revolution gets interesting. PCIe took over 5 years to develop the Gen4 technology at 16 Gbps, but rather than be satisfied with those speeds, it has announced PCIe Gen5 with speeds of 32 Gbps. So, in a matter of a year, we have seen server speeds go from 16 Gbps to over 30 Gbps, and the technologies are looking to PAM4 to push speeds above 50 Gbps. We have also moved from having one dominant technology to having competition in the technology space, which can lead to even further innovation.

Of course, the revolution does not happen without challenges. For PCIe Gen4, the standard eye height was specified at a mere 16 mV at the end of the channel (this is really small), even with all channel effects removed and equalization applied. Going to 32 Gbps does not help that problem, and for Gen5, the eye height drops to a miniscule 8 mV. Essentially, high-speed digital technologies are moving to a closed eye.

With Keysight’s PCI Express technology expert Rick Eads having been elected to the PCI-SIG Board of Directors this month, we’ll be the first to update you on the latest developments on PCIe Gen5…  and of course we’ll  provide you with the appropriate tool sets for the next testing challenges.

stmichel

What to Expect From DDR5?

Posted by stmichel Employee Jun 12, 2018

#DDR  #DDR4 #DDR5 #DRAM #RAM

 

DDR4 was the first DRAM technology to break the High Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This webcast will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.

 

Get prepared for DDR5 with this webcast.

 

Find out more about Keysight DDR solutions.

Setup of integrated coherent receiver test

 

 

The test of an integrated intradyne coherent receiver (#ICR) as defined by Optical Internetworking Forum requires many

parameters to test for each device. These devices can be tested in the above illustrated setup quickly and easily. Again the EVM concept offers a powerful tool to verify the overall quality of an ICR within a second. This setup simulates a #golden transmitter which has better performance than any production-series transmitter. Analyzing this signal in the same way as a normal transmitter signal can reveal impairments that reflect the intrinsic performance of the ICR under test (see left screens in the screen shot below) and therefore indicates limitations to the performance

that can be achieved.

 

In addition to the spectral display on the right screens, the #image suppression gives you an indication of distortions in the system and shows how well balanced your photodiodes are.

 

Screenshot - performance verification

 

For detection of complex modulated optical signals #OIF defined an electro-optical component typically described as integrated dual polarization #intradyne coherent receiver (ICR). This component contains optical and electro-optical components in one package.

 

The hybrid contains many components that need to be integrated and perform seamless as a black box coherent receiver.

The integrated component needs to be tested in research and in manufacturing.

 

The M8290A offers an application (M8290430A), to test this kind of devices and extract parameters that characterize the behavior of the component.

 

With the M8290A it is possible to test the component in an environment that is identical to the final application providing

highest confidence in the performance of the component:

 

  • This test is performed with the M8290A by generating a beat signal within the detection band to the ICR optical inputs using two continuous wave tunable laser sources.
  • This test is an excellent setup to verify the intrinsic performance of the ICR as it reflects noise impairments and all kinds of distortions.
  • The IQ diagram gives an indication on the noise and the distortion of the signal of the ICR created from a nearly perfect beat signal. The same parameters that are used to quantify the signal quality (EVM, IQ offset, IQ imbalance, Quadrature error) can be used to qualify the intrinsic performance of the component.
  • #Image suppression in a spectral display gives a good indication of presence of imbalances between channels and PIN diodes in the coherent receiver. A good image suppression and large common mode rejection ratio indicate a well balanced receiver.

 

ICR Image Suppresion Screenshot

 

Image suppression is an excellent indication of the presence of potential distortions within the optical receiver. An image

suppression in the order > 35 dB indicates high CMRR of well balanced PIN diodes and well de-skewed I-Q channels in the ICR under test.

 

EVM is an excellent indicator of the overall quality of a complex modulated signal. This concept is applied in that test by creating a beat signal in the ICR and analyzing it in the same way as a complex modulated signal. This emulates a kind of ideal stimulus of the ICR. With this test the EVM can be measured at a single frequency point along the receiver  bandwidth of the device under test and within the digitizer bandwidth. This measurement provides additional insight to the device under test, ensuring distortion-free measurements at each tested frequency point with good EVM.

 

ICR Frequency Response Screenshot

 

Integrated coherent receiver test provides most relevant test parameters as defined by OIF to characterize integrated coherent receiver components. The following test results are provided by the software:

 

  • Frequency response S21(f) for each tributary
  • Phase difference between I and Q as function of frequency for X and for Y polarization
  • Quadrature angles between I and Q for each polarization plane X and Y
  • Gain imbalances
  • Receiver skew values
  • Error vector magnitude (EVM % rms) over frequency (in addition to OIF)
  • Image suppression over frequency (in addition to OIF)

 

Coherent optical devices such as dual-polarization IQ modulators and intradyne coherent receivers need to be tested in their different development stages as well as qualified by the system integrators. The optionally available coherent optical device test software (M8290440A) provides a turn-key solution for the characterization of these devices. One user interface provides control of all instruments through a single software package. None of the tests requires

reconnecting the DUT, saving test time and reducing the uncertainty introduced by connecting and reconnecting the device. The coherent optical device test license provides:

 

  • S21 magnitude responses for XI, XQ, YI, and YQ
  • S21 phase responses for XI, XQ, YI, and YQ
  • IQ skew for X and for Y polarization
  • XY skew
  • Receiver IQ angle for X and for Y polarization (requires a two-laser setup)

 

Amplitude and Phase Response Screenshot

 

The test is based on generating a broadband multi-tone signal using a Keysight arbitrary waveform generator (AWG), e.g., M8196A. Comparing the received amplitudes and phases of each tone with the known original amplitudes and phases, the frequency and phase response of the device under test (DUT) can be reconstructed as shown in the figure below . From the measured phase response of each tributary, it is possible to calculate the individual group delays as well as the relative skews.

 

 Frequency and Phase Reconstruction Principle - Diagram

 

 

 

Setup for sequential testing of a device having both transmit and receive functionality, e.g., #IC-TROSA, #ACO, etc. The transmit-side is re-used after being characterized in the first step to generatethe test signal for the receive side.

 

    Block Diagram of Setup for Sequential Transceiver Testing

 

 

 

 

Setup for testing optical #IQ modulators. This test can also be used as an in-system calibration measurement. The resulting frequency responses can be exported as S-Parameter files and used for pre-distortion of complexly modulated data signals using QPSK or QAM formats.

 

Block Diagram of Setup for Testing Optical IQ Modulators

 

 

 

 

Setup for testing coherent receive devices as for example ICR modules. In contrast to the ICR test application (M8290430A), this test provides additionally the absolute phase response of each receiver path (XI, XQ, YQ and YQ) and allows to derive the respective group delay individually.

 

Block Diagram of Setup for Testing Coherent Receive Devices

 

 

 

 

www.keysight.com/find/oma

With demand on networking and computer performance increasing at a rapid pace, there is a growing need to store, move and process more data in real-time than ever before. As data speeds increase, channel attenuation becomes an inhibitor to moving data across an interface bus. This webcast will highlight Keysight’s contributions with PCIe® 4.0 technology for physical layer transmitter and receiver testing. Topics will include improvements to the PCI Express 3.0 CEM connector to support 16 GT/s signaling, improvements to receiver testing methodologies for paving the way to PCI Express 4.0.

 

Join Keysight’s Rick Eads , an active contributor within the PCI-SIG workgroup, for a 1-hour webcast  on January 17  to learn more about:

  • The key challenges of developing a #PCIe 4.0 link capable of 16GT/s operation
  • The changes to the channel and connector interface that are needed
  • The tools available to help characterize and debug PCIe 4.0 transmitters and receivers

 

  Rick Eads - Keysight's active contributor  to the PCI-SIG workgroup   Join Webcast.

If you don't see the webcast in the list, click onSelect Country and select 'US'.

Historically, intensity modulation and direct detection have been used in #optical communications to transmit information. This scheme is still used for short reach applications; however, the spectral efficiency and data rate is very limited. For example, a #100 Gbps signal using an intensity modulation scheme requires either very large bandwidth components or parallel transmission of several lower speed signals.

To support the high data rates required by today’s applications, modern communications systems must provide capabilities beyond traditional intensity modulation and direct detection schemes. Increasing demand for bandwidth has pushed the telecom industry to use coherent transmission techniques. Coherent data transmission takes advantage of amplitude, phase and polarization characteristics of light to enable transmission rates of #200 Gbps and more by transmitting complex symbols, each carrying multiple bits of information.

In addition to speed, small size and low power consumption are key requirements for the circuit design. To address these needs, new integrated analog coherent optics modules (ACOs) and digital coherent optics modules (DCOs) have been developed and are being used in many network systems. The modules feature integrated abilities for both transmission and reception in a standardized pluggable module and include these sub systems:

  • Narrow linewidth laser source,
  • Polarization-multiplexed IQ modulator (PMQ), and
  • Intradyne coherent receiver (ICR)

 

An implementation agreement for an integrated component containing all those sub-systems is currently being developed within the optical internetworking forum (OIF) and is called IC-TROSA (Integrated Coherent Transmitter-Receiver Optical Subassembly). Finding alignment on the interface specifications between the coherent optical devices and the DSP is a challenging task that requires a lot of testing. These tests are comprised of device characterizations as well as system performance measurements.

Any coherent transceiver requires a digital signal processor (DSP) to code and decode the coherent signal. Specifications for the interface between the coherent optical devices (or the ACO module) and the DSP are critical for achieving error-free data transmission. The difference between the ACO and DCO concept is that for DCOs, there is a permanent connection between the coherent optical devices and the DSP, while for ACO, there is a pluggable interface between coherent optical devices and the DSP.  

Finding alignment on the interface specifications between the coherent optical devices and the DSP is a challenging task that requires a lot of testing. These tests are comprised of device characterizations as well as system performance measurements.

 

Amplitude and Phase Response -  Screenshot of M8290440A Test Solution for Coherent Optical Transmit and Receive Devices

   

Testing coherent optical transmit devices or assemblies requires stimulating electrical signals, generated using a high-speed arbitrary waveform generator and suitable software. The resulting optical output signal is received and analyzed using an optical modulation analyzer (OMA). For the receive side coherent optical devices or assemblies, an optical stimulus, which can either be a reference signal or an unmodulated tunable laser, and a high-speed digitizer with the same analyzing functions as the OMA is needed. Performing automated tests with the same set of equipment without intermediate reconnections saves time and ensures repeatable results. The Keysight M8290A Optical modulation analyzer High-speed digitizer test solution is an example of integrated hardware and software optimized to perform coherent optical device test.

Watch this video on high-speed coherent component and system test.                                                                          

 

   

 

 

 

Data centers are growing to meet customer demands for higher bandwidth. The #100GBASE-KR/CR backplane and copper interfaces help solve these higher demand issues. However, a faster Ethernet backplane means greater challenges for engineers. The link training decoder helps engineers to manage system integration problems.

 

The new N8851A solution supports 100GBASE-KR/CR systems integrators who work with #Ethernet backplane and copper technology. This decoder provides important link training information that addresses issues from channel loss and system integration.Customers using backplane technologies can use this decoder to troubleshoot issues between different 100GBASE-KR/CR vendor solutions.

 

Get 64b/66b decoder along with a link training decoder in one solution - screenshot

 

The N8851A is the only solution today with both 64b/66b decoder along with a link training decoder. The N8851A solution enables engineers to decode 64b/66b data and link training data in less than 30 seconds.

The #link training signaling, also known as Differential Manchester Encoding (DME), provides detailed information on control channels such as status update and coefficient registers.

 

This solution includes a suite of configurable protocol-level searches and software-based triggering specific to 64b/66b and link training of Ethernet technologies such as 100GBASE-KR/CR. The N8851A is the only tool that allows for 64b/66b decoding and link training in one solution.

 

The multi-tab protocol viewer includes correlation between the waveforms and the selected packet, enabling users to quickly move between the physical and protocol layer information using the time-correlated tracking marker. The 64b/66b and link training decoder is compatible with 100GBASE-KR/CR Ethernet busses.

 

Find out more.

Silicon Photonics - Optical Test on  PCB, wafer, IC and chip

 

 

Progress in photonic integrated circuit (#PIC) technology and applications is accelerating with the onset of an industrial ecosystem comprised of #InP and #SiP foundries, commercial modeling tools, and photonic test capability. Bringing optical test deeper from package level into the semiconductor process is an important step to assure performance and yield.  A key aspect of testing at the wafer, bar and chip stage is fast reproducible optical coupling, including probe-position optimization and polarization alignment. Advanced methods and instruments developed for the fiber optic communications industry are now being adapted for this new environment. In this webcast, we will give an introduction to PICs and the silicon photonic industry as well as current challenges which must address a mixture of DC, RF and photonics testing.

 A new webcast recording provides insights into the basic considerations in #silicon photonic test.

 

Watch webcast.

 

Topics covered here:

 

  • What are Photonic Integrated Circuits (PICs)?
  • 2.54 Tb/s Network on a Chip
  • Photonic IC Waveguides
  • PIC Design Flow
  • Finding PIC Defects
  • Test Laser Sources
  • Optimizing Measurements  for High Dynamic Range Lasers
  • Wavelength Testing Photodetectors
  • Responsivity versus Wavelength and Polarization
  • Complete Optoelectronic Test
  • Wafer Level Photonics Probing
  • Probe Design

 

 

 

 

 


Moving to the next higher data speed class of #400 Gbps or# 600 Gbps, the question is again how transmission efficiency can be further increased.

In the #optical communications world, capacity gains come essentially from three variables: more carriers through techniques such as polarization and multi-carrier #OFDM modulation, better spectrum efficiency through higher modulation density and higher symbol rate (Figure 1).

Increasing data throughput by increasing symbol rate, number of bits per symbol or number of carriers

Figure 1. Factors contributing to optical system capacity.


Testing these higher order systems with data rates close to #1 Tbps requires test equipment capable of clean signal generation and analysis and a measurement bandwidth of at least 20 GHz, to be sure the measurements represent system performance, not the limitations of the test equipment. The instruments must offer the flexibility to address many different #modulation schemes on 4 synchronized channels for a dual-polarization I/Q signal. Traditionally, receiver tests such as #phase noise, observed #signal to noise ratio and polarization tests have been performed using a “gold” transmitter, giving a view of the device but lacking completely deterministic knowledge (Figure 2).

 Traditional optical receiver test setup

Figure 2. Traditional optical receiver test setup.


Using an arbitrary waveform generator (AWG) such as the Keysight M8196A allows the creation of test signals in the electrical domain, including both clean signals and signals with specific, known, impairments. For transmitter test, these can be fed directly to a transmitter and the resultant error rate can be measured directly. For receiver test, they can be used directly to test #DSP stages and be translated to the optical domain to create both clean and stressed deterministic optical signals for full receiver test. (Figure 3)

 Optical transmitter and receiver test scenarios using an arbitrary waveform generator

Figure 3 . Optical transmitter and receiver test scenarios using an arbitrary waveform generator.

 

The key challenges in making measurements on #coherent optical systems lie in providing known, repeatable clean and distorted test signals at data rates in excess of 32 GBaud and with the flexibility to support diverse modulation formats. Test system calibration should be possible, not only at the front panel of the test signal generator and measurement equipment, but at any point in the signal chain through embedding and de-embedding techniques using the transmission system’s S-parameters.

Figure 4 shows an example of measurements across an entire communications channel, showing the ability to measure cumulative effects using the Keysight N4391A or N4392A Optical Modulation Analyzers.

Cumulative optical modulation analysis using a Keysight N4391A or N4392A optical modulation analyzer


Figure 4. Cumulative optical modulation analysis using a Keysight N4391A or N4392A optical modulation analyzer.

Read the complete application note and find out about how to face higher-speed challenges in signal calibration, quality measurements and troubleshooting.

 M8040A - 64GBaud High-performance BERT

 

Today’s data center infrastructure is continuously optimized to address bandwidth capacity growth, power, reach and service differentiation. Higher transmission rates, more transmission lanes and new multi-level data formats like PAM-4 address the increased transmission bandwidth demand for the next generation data center interconnects. The latest revisions of #IEEE 802.3 bs and #OIF CEI-56G implementation agreements define PAM-4 and NRZ interfaces for electrical chip-to-chip, chip-to-module, backplane connections and #optical interfaces for up to 400 Gbit/s bandwidth. R&D and validation labs who need to characterize receivers for data center interconnects with PAM-4 or NRZ signal formats and data rates up to #64 Gbaud are facing new test challenges, such as tighter timing margins, channel loss, non-linearity, level interference and crosstalk effects, making test efficiency and accuracy essential. Channel loss and reflections in electrical interconnects like #chip-to-chip, #chip-to-module interfaces and #backplanes, create more and more challenges with increasing symbol rates for the design and test of transmitters and receivers. One commonly used technique to overcome the channel loss dilemma is the use of digital pre-distortions in the transmitter and equalization in the receivers.

 

Equalizers

Equalization in the receivers helps to reopen closed eyes by removing the intersymbol interference (ISI). The amount of ISI depends on the physical distance, the material of the PC board trace or cable, the symbol rate and the transmitted patterns. The ability to adjust the amount of equalization to the real channel conditions is therefore mandatory. The new #M8040A is the latest member of the modular AXIe based M8000 series of BER test solutions. It is a highly integrated BERT that supports #PAM-4 signals up to #64 Gbaud and NRZ signals up to #64 Gbit/s. The pattern generator module provides built-in de-emphasis, jitter injection and an optional second channel. Engineers and designers can select PAM-4 and NRZ in the user interface, eliminating the need for external combiners, cabling and deskew to provide PAM-4 signals. For best signal quality, remote heads reduce the distance to the device under test. The analyzer module provides true PAM-4 #error analysis in real-time for long PRBS and QPRBS patterns. The built-in and adjustable equalizer is a new option of the analyzer that helps to open closed eyes on the loopback channel. The analyzer now also supports symbol rates up to 64 Gbaud for NRZ signals. This ensures proofing even low bit error ratios and symbol error ratios with the required confidence. Users can control the M8040A from a graphical and remote control interface.

 

M8040A - 64GBaud High-performance BERT Channel Loss over Frequency

 

Adjustable equalization in the error analyzer helps to re-open closed eyes caused by the loss of the loopback channel. The image illustrates channel loss over frequency. Depending on NRZ or PAM-4 coding and the Nyquist frequency of the received pattern the maximum range of the available equalization can vary.  

 

More information about the Keysight M8040A 64 GBaud BERT:

M8040A on Keysight.com

 M8040A Datasheet  

 

Application Note - Equalization: The Correction and Analysis of Degraded Signals

Video: Simplify PAM-4 receiver test with Keysight M8040A 64 GBaud high-performance BERT 

Master 400G - Free Poster on 400 Gb/s Solutions

The combination of the spectral efficient PAM4 modulation together with the mature direct modulation / direct detection technology has been chosen by the #802.3bs and #802.3cd task forces [i] to address the urgent demand for more capacity and accelerating cost-per-bit reduction in intra and inter data center communication links. The shift from NRZ to #PAM4 modulation enables to double the line rates compared to optical #100Gigabit Ethernet transceivers while keeping the modulation speed at 26.56125Gbaud [ii]  and therefore to leverage some of existing #100G components.  

Consequently, the compliance test procedures considered for next-generation #400GBASE transceivers are similar to the ones adopted for NRZ-based #100GBASE transceiver but with following noticeable differences:   A new #TDECQ metric[iii] is employed to characterize the quality of a transmitted/received signal instead of the classical eye mask analysis. In addition, a digital reference equalizer is required to compute various signal metrics during transmitter performance testing or during stress signal calibration for receiver stress testing. Finally, the optical transceiver is not expected to operate error-free any more - neither under the stress conditions defined by the standards nor in typical usage.

The latter point is a consequence of the significant sensitivity penalty (>9dB) resulting from the shift from NRZ to PAM4. This aspect affects the transceiver design, performance test and compliance in different ways: A Reed-Solomon forward error correction (#FEC) scheme is required. It is often located on the line-card and consequently not considered in the transceiver test procedures. Furthermore, over-dimensioning the transceiver design to ensure enough margin is not possible any more as the requirements for the components (direct modulated laser, integrated MZM, photodiode, driver and trans-impedance amplifier) in terms of noise, dynamic range and bandwidth are already very stringent. Careful design is therefore necessary to achieve the target performance using existing #100G optical components. Finally, accurate, stable and repeatable stress signal calibration () is required to ensure a reliable transceiver qualification process.

: Unstressed  and stressed  26Gbaud PAM4 signal according to the 400GBASE-FR8 recommendations (as of June 2017).

Unstressed (left) and stressed (right) 26Gbaud PAM4 signal according to the 400GBASE-FR8 recommendations (status of June 2017).

 

Achieving this is not a trivial task as the combination of different stress factors (inter symbol interference, jitter,

Gaussian noise, optical power level) has complex dependencies on the target metrics (figure below).

 

100/ 200/ 400GBASE Optical Stress Test Solution - Stressed Eye Signal Calibration Workflow

 

Keysight solutions for 400G optical transceiver testing address all these challenges. For instance, Keysight will showcase a fully automatized stress signal calibration and DUT compliance performance test for PAM4-based #transceiver testing at ECOC in Goteborg. This solution, based on the high performance BERT M8046A #64Gbaud and DCA-M scope, addresses the needs of R&D and QA engineers working on the next generation of optical transceivers.

For more information:

N4917B Optical Receiver Stress Test Solution

Blog: The Basics - Optical Receiver Stress Test

 

 

[i] “802.3bs  200 Gb/s and 400 Gb/s Ethernet Task Force” and  “802.3cd, 50 Gb/s, 100 Gb/s and 200 Gb/s Ethernet Task Force”

[ii] Some flavors of the a.m. standard drafts also consider a doubling of the symbol rate to 53.123GBaud, resulting in a line rate of 106Gb/s. 

[iii] King, Jonathan, David Leyba, and Greg LeCheminant. "TDECQ (transmitter dispersion eye closure quaternary) replaces historic eye-mask and TDP test for 400 Gb/s PAM4 optical transmitters." Optical Fiber Communication Conference. Optical Society of America, 2017.

#Optical coherent transmission, initially used in long-haul transmission, is getting deployed in #metro networks, and is expected to make its way to #data center interconnects. Each product generation increases transmission speed by moving to higher symbol rates and higher-order #QAM constellations. Today’s 100G systems that use quadrature phase shift keying (QPSK) at 32 GBd will evolve to 400G by doubling both the bits per symbol and the symbol rate, i.e., using 16-state quadrature amplitude modulation (16QAM) at #64 GBd.

 

At the same time, the industry strives to reduce size, cost, and power consumption of the transceiver hardware. The higher complexity of the transmission schemes combined with the new challenges that result from the dense electronic and photonic integration leads to tighter requirements and lower performance margins for all the components as well as the assembled transceivers. To achieve this, more testing is required during development, NPI and production.

 M8290A Optical Modulation Analyzer and High-speed Digitizer Test Solution

The new M8290A rack-mountable modular coherent test system for the AXIe platform is designed to address the 400G speed class in a significantly narrower form factor and a more attractive price point than today’s oscilloscope-based solutions for this speed class.

 

For coherent transmitter and receiver testing, the optical modulation analyzer module M8292A and the #digitizer module M8296A fill the gap between the compact and affordable N4392A integrated #optical modulation analyzer for 100G and the real-time oscilloscope-based N4391A optical modulation analyzer supporting speed classes of 400G, 600G and Terabit per second.

 

The novel compact and modular approach makes the M8290A an ideal system for coherent transmitter qualification and debugging using error vector magnitude (#EVM) and related parameters as well as for component characterization like #ICR, #PMQ or even fully assembled #CFPx-ACO modules. The concept addresses the needs of development teams, new product introduction (NPI) groups and production test engineers, looking for compact and affordable test equipment for 400G . The M8290A modular coherent test solution provides the flexibility and scalability to choose an optical module for characterizing transmitter components and/or an electrical module for characterizing receiver components. In the same platform, it is further possible to add one of Keysight’s high-speed arbitrary waveform generators to combine timulus and response testing in one AXIe mainframe. This makes the M8290A an optimal combination of compactness, affordability sand performance that cannot be achieved with current oscilloscope-based solutions in this speed class.

 

Experience the solution live at ECOC.

In addition to USB, the Type-C connector allows implementation of Alternate technologies like DisplayPort, Thunderbolt, and HDMI.

 

A recent announcement from Intel will radically change future generations of Type-C implementations: https://newsroom.intel.com/editorials/envision-world-thunderbolt-3-everywhere/

 

We will focus on the 2 key points of this announcement and how it will affect you:

  • Thunderbolt Integrated CPU
  • Thunderbolt Open Spec

 

Some of the resistance for Thunderbolt 3 adoption included higher costs, proprietary technology, and severe signal integrity (SI) challenges at 20 Gbps. The Intel press release will ultimately remove the first 2 barriers to entry by reducing cost and removing the royalty fee. But it still does not change the SI challenges inherent in a high-speed 20Gbps link over passive cables.

 

To get a head-start on Thunderbolt 3 development, first step is to register to be a member and get the latest Specification and Compliance Test Specification (CTS) at:  https://thunderbolttechnology.net/

In addition to getting the Spec documents, membership allows you access to 3 Plugfests a year where you can register your product to be tested, plus get the latest updates on the technology.

 

Since the Spec is not currently publicly available, we want to view Thunderbolt 3 through the lens of: How to Transmit, Traverse a passive cable, and Receive at the other end a 20Gbps signal running over a 80Gbs port with crosstalk. That is essentially the challenge of implementing Thunderbolt 3.

 

The legacy Thunderbolt/Thunderbolt 2 technologies were fairly simple to test because they used an active cable with open eyes at the Transmitter and Receiver. Thunderbolt 3 incorporates a passive cable which makes testing significantly more complex.

 

Let us now look at the methodologies and testing required to successfully implement Thunderbolt 3.

 

Transmitter Equalization

Like PCIe Gen 3 and USB 3.1 Gen 2, Thunderbolt 3 requires TXEQ to compensate for a lossy channel. There is a table of Thunderbolt 3 TXEQ Presets that must first be characterized to ensure they are precisely outputting the correct Pre-Shoot and De-Emphasis for each specific Preset. Next step is to perform a Preset Calibration/Optimization where a specific Preset is chosen as the best Preset for your particular Transmitter implementation.

 

Receiver Equalization

There is a set of CTLE DC Gains that need to be applied to determine the optimal performance. After determining the optimal CTLE, an optimal DFE also has to be applied to determine the best RXEQ for your particular channel. Not optimizing this parameter will guarantee a failure when implementing the passive cable use case.

 

Legacy 10.3125 Gbps Compatibility

Thunderbolt 3 allows inter-operability with legacy Thunderbolt 2 products connected with an adapter cable. As a result, you will need to test at both the Thunderbolt 3 20.625 Gbps rate and also the Thunderbolt 2 10.3125 Gbps rate.

 

Type-C Operation

Thunderbolt 3 runs exclusively over the Type-C connector. Since the Type-C connector has a CC1 and CC2 side, you will need to test both the TX1/RX1 pairs as well as the TX2/RX pairs - 4 differential pairs in total. Depending on a single, dual, or quad(!) port implementation, you will also need to test additional Type-C ports.

 

TP1/ TP3EQ Test Points

The TP1 test use case relates to using a passive cable. The TP3EQ use case is when your customer uses a passive cable. If your implementation prevents direct access to TP1, you must de-embed the channel to TP1 due to significant signal loss at 20 Gbps. Similarly, you must implement or embed the compliant cable model when testing at TP3EQ for 10G or 20G use cases.

 

Signal Quality Tests

Many of the Thunderbolt 3 measurements at first glance may seem familiar – UI, SSC, Rise/Fall, Jitter, and Eye Diagram. However, the underlying methodology for specifics like SSC Phase Slew Rate, CDR Order, PLL Loop BW and Damping, CTLE, DFE, and Uncorrelated Jitter are very unique and detailed in the CTS.

 

Requirements for USB-PD and Other Technologies

As shown in Figure 1, Thunderbolt 3 provides power up to 100W. This is a capability associated with USB-PD. Thunderbolt 3 is an Alternate mode that runs over the USB Type-C connector. As a result, it must adhere to the rules and testing related to the USB Type-C and USB-PD specifications. Both these specs are available from the USB-IF at: www.usb.org.

 

Figure 1 also shows that Thunderbolt requires implementation of USB and DP. Testing specifics for USB are available from www.usb.org and DP details from www.vesa.org.

Thunderbolt 3

I hope this blog provides a brief introduction to preparing for your Thunderbolt 3 implementation. I will share more specific testing details once the Thunderbolt 3 Specification becomes public.

 

USB Type-C™ and USB-C™ are trademarks of USB Implementers Forum

ThunderboltTM are trademarks of Thunderbolt Technology Community

As people use more applications on their phones, tablets, computers, and Internet of Things (IoT) devices, the  network needed to deliver the data is constantly being upgraded for the constantly increasing bandwidth demand. Four-level pulse amplitude modulation (PAM-4) signaling is a leading contender for implementing the 56G lane data rate which will enable 400G links for the next upgrade in network bandwidth.

#PAM-4 is gaining traction for high-speed #SerDes links over an electrical backplane, especially for designs attempting to deliver greater than #56Gbps throughput. Doubling data rates with traditional non-return to zero (NRZ) signaling is technically challenging due to the extremely signal loss at high frequencies. The alternative signaling technique, PAM-4, is used to transmit at 28Gbaud, but with 4 amplitude levels (where each symbol represents 2 bits), effectively delivering 56Gbps throughput.

 

From 10 to 56 G

 

Conventional impairments such as jitter, noise, channel loss, and inter-symbol interference (ISI) have more complicated expression with PAM-4. In addition to this, receiver architectures for PAM-4 introduce new concepts for system designers such as:

  • 3 Slicer outputs with time-varying voltage thresholds (for deciding which amplitude level has been received)
  • Individual Slicer Timing Skew (each Slicer's decision point can be offset in time from the other two)
  • Multi-tap decision feedback equalization (#DFE)
  • #Clock and Data Recovery 

The complex interaction of these new concepts influences specific design trade-offs for PAM-4.

 

Keysight’s Advanced Design System (ADS) offers a design space with a channel simulator, accommodating not only lumped-element models but also the distributed transmission line, S-parameter, and EM models that are essential to model high-speed PCB traces and determine ultralow #BER contours in seconds not days.

 

How to send data at 56 Gbps

The ADS #channel simulation enables a comparison of PAM-4 versus NRZ technology. This example demonstrates the trade-off of price vs performance in #PCB design. Cheaper PCB materials with more loss and no-back-drilling of vias are more likely to exhibit resonances at higher frequencies. This channel may not support NRZ to 56Gbps, but will support PAM-4 more easily, if the resonances are higher in frequency than the main spectral content of the #PAM-4 signal.

 Adaptive DFE

The system designer attempting to compare NRZ to PAM-4 trade-offs needs to use PAM-4 IBIS-AMI models from SerDes vendors within their channel simulation. Keysight Technologies' continuing leadership in the IBIS Open Forum, Keysight EEsof EDA now offers support for the new IBIS v6.1 specification. Developed in collaboration with the industry's leading PAM-4 SerDes IC vendors, the ADS Channel Simulator provides a trusted bit-by-bit simulation engine for PAM-4

 

Join us at ECOC in Gothenburg to experience this solution live

 

Where to find more information:

For more information on PAM-4 solutions from Keysight Technologies, refer to http://www.keysight.com/find/pam4