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Partial Reconfiguration: the backbone of HVI

Blog Post created by jakedaly Employee on Nov 7, 2018

Until recent years, synthesis of FPGA images was binary (no pun intended): reconfiguration was an all or nothing sort of thing. If you wanted to change something about your design—even something as simple as adding a register—you had to rebuild the entire image. This was time consuming, inefficient, and above all frustrating for engineers who wanted to make small changes to designs: rebuilding an image for a complex design could take hours.

 

Vendors realized this, and developed a method for being able to make small incremental changes to designs. With partial reconfiguration, certain areas of the FPGA-floor are “locked” so to speak, while the designer implements changes on other, smaller areas of the floor. The result is that it is much quicker (orders of magnitude) to implement these changes on a smaller scale than it is to reconfigure the entire FPGA.

 

As partial reconfiguration becomes more and more the norm for FPGA technology, digital designers are finding new ways to take advantage of it—and not just statically. What if it were possible to implement some logic in the FPGA, process some data, and then based on that data, quickly reconfigure the FPGA to process a next batch of data in a slightly different way? This is where digital technology is headed, and how Keysight’s own HVI technology is evolving. The graphical entry method will soon be subsumed by programming libraries that will allow users to program HVI in the same location that instrument control and data will be flowing into and out of.

 

For quantum computing applications, this sort of dynamic reconfiguration is extremely useful. Qubits are extremely sensitive to their environments: both minor variations in the phase and magnitude of control pulses can superpose the qubit into completely different states. HVI technology attempts to circumvent this via partial reconfiguration. Normally, a designer would have to be concerned about how tightly all channels in the system were synchronized. Across many channels and many chassis, triggering and skew quickly become an issue.

 

With HVI and partial reconfiguration, all of these pulse sequences are triggered on each channel digitally. There is no skew, it scales up flawlessly across many channels and chassis, and the only real limitation on how resolved the pulse sequences can be is sampling rate of the AWG itself. All of this is possible because partial reconfiguration allows the HVI engine to compile these pulse sequences and virtual instrumentation in one small, sectioned off area of the FPGA, making it so this can be done instantaneously and on-the-fly.

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