FrankC

Calculating the Maximum Acquisition Time for a Single Record

Blog Post created by FrankC Employee on Jul 12, 2018

So how do I calculate the maximum single record acquisition time for my digitizer?  There are some obvious factors, such as acquisition memory size, sample rate, and the number of bytes (or bits) per sample.  However, some other factors aren’t so obvious, such as the effect of using an external clock, using DGT mode with binary decimation, or using DDC mode (an available option for M9203A and M9703B).

 

This article explains how to calculate maximum acquisition time using these factors, highlighting any restrictions that have to be taken into account.

 

 

M9203A and M9703B: DGT Mode

 

Maximum acquisition time in DGT mode is calculated as:

Time = (Memory Bytes Per Channel) / (Sample Rate * Bytes Per Sample)

 

Memory Bytes Per Channel:

Acquisition memory depends on the installed option:

  • M9203A-M02 and M9703B-M10: 128 MB/Ch (134,217,728 bytes)
  • M9203A-M10 and M9703B-M40: 512 MB/Ch (536,870,912 bytes)
  • M9203A-M40 and M9703B-M16: 2048 MB/Ch (2,147,483,648 bytes)

 

Sample Rate:

Internal sample rate depends on model/option:

  • M9203A has an internal sample rate of 1.6 GS/s (-SR2)
  • M9703B has two options for internal sample rate; 1 GS/s (-SR1), or 1.6 GS/s (-SR2)

 

Can be decreased via an external clock:

  • Sample Rate = External Clock Frequency / 2
  • Min Clock = 1.8 GHz; Max Clock = 2 GHz (-SR1) or 3.2 GHz (-SR2)

 

Can be decreased via binary decimation:

  • Decimated Sample Rate = Sample Rate / 2n
  • M9203A: n = integer in the range 1 to 10
  • M9703B: n = integer in the range 1 to 8

 

Binary decimation can be combined with the external clock to reduce the sample rate even further.

 

Bytes Per Sample:

ADC resolution is 12 bits, with 4 bits added to each sample to account for correction/scaling; every sample therefore requires 16 bits (2 bytes).

 

RESTRICTION:

Single record acquisition time is limited to 236 clock cycles.  This includes decimated clock cycles, so there are some cases where maximum acquisition time is reached before memory is full – maximum acquisition time is reached at decimation ratio 26 for M9203A-M40 and M9703B-M16.  Decimation greater than 26 will still decrease the sample rate, but won’t increase acquisition time.

 

Examples: M9203A/M9703B, DGT Mode

  • Maximum memory, no external clock, no binary decimation
  • Maximum memory, minimum external clock, no binary decimation
  • Maximum memory, no external clock, 26 binary decimation
  • Maximum memory, minimum external clock, 26 binary decimation

 

M9203A-SR2 and M9703B-SR2

Memory/Channel
(Bytes)

Ext. Clock
(Hz)

Decimation

Sample Rate (Sa/s)

Bytes/
Sample

Time (Secs)

2,147,483,648

N/A

N/A

1,600,000,000

2

0.67108864

2,147,483,648

1,800,000,000

N/A

900,000,000

2

1.19304647

2,147,483,648

N/A

64

25,000,000

2

42.94967296

2,147,483,648

1,800,000,000

64

14,062,500

2

76.35497415

M9703B-SR1

Memory/Channel
(Bytes)

Ext. Clock
(Hz)

Decimation

Sample Rate (Sa/s)

Bytes/
Sample

Time (Secs)

2,147,483,648

N/A

N/A

1,000,000,000

2

1.07374182

2,147,483,648

1,800,000,000

N/A

900,000,000

2

1.19304647

2,147,483,648

N/A

64

15,625,000

2

68.71947674

2,147,483,648

1,800,000,000

64

14,062,500

2

76.35497415

 

 

M9203A and M9703B: DDC Mode

 

Maximum acquisition time in DDC mode is calculated as:

Time = (Memory Bytes Per Channel) / (Sample Rate * Bytes Per I/Q Sample)

 

Memory Bytes Per Channel:

See previous section (DGT mode).

 

Sample Rate:

Internal sample rates are described in the previous section (DGT mode).

 

Sample rate is always decimated in DDC mode, but the ratio range is different from DGT mode:

  • Decimated Sample Rate = Sample Rate / 2n
  • n = integer in the range 2 to 19

 

DDC decimation can be combined with the external clock to reduce the sample rate even further.

 

Bytes Per I/Q Sample:

DDC decimation ratio = 22; every I/Q sample requires 4 bytes

DDC decimation ration > 22; every I/Q sample requires 8 bytes

 

RESTRICTION:

Maximum acquisition time is achieved at DDC decimation ratio 28.  Decimation greater than 28 will still decrease the sample rate and analysis bandwidth, but won’t increase acquisition time.

 

Examples: M9203A/M9703B, DDC Mode

  • Maximum memory, no external clock, 22 DDC decimation
  • Maximum memory, no external clock, 28 DDC decimation
  • Maximum memory, minimum external clock, 22 DDC decimation
  • Maximum memory, minimum external clock, 28 DDC decimation

 

M9203A-SR2 and M9703B-SR2

Memory/Channel
(Bytes)

Ext. Clock
(Hz)

Decimation

Sample Rate (Sa/s)

Bandwidth
(Hz)

Bytes/
Sample

Time (Secs)

2,147,483,648

N/A

4

400,000,000

320,000,000

4

1.34217728

2,147,483,648

N/A

256

6,250,000

5,000,000

8

42.94967296

2,147,483,648

1,800,000,000

4

225,000,000

180,000,000

4

2.38609294

2,147,483,648

1,800,000,000

256

3,515,625

2,812,500

8

76.35497415

M9703B-SR1

Memory/Channel
(Bytes)

Ext. Clock
(Hz)

Decimation

Sample Rate (Sa/s)

Bandwidth
(Hz)

Bytes/
Sample

Time (Secs)

2,147,483,648

N/A

4

250,000,000

200,000,000

4

2.14748365

2,147,483,648

N/A

256

3,906,250

3,125,000

8

68.71947674

2,147,483,648

1,800,000,000

4

225,000,000

180,000,000

4

2.38609294

2,147,483,648

1,800,000,000

256

3,515,625

2,812,500

8

76.35497415

 

 

M9709A

 

Maximum acquisition time is calculated as:

Time = (Memory Bytes Per Channel) / (Sample Rate * Bytes Per Sample)

 

Memory Bytes Per Channel:

Acquisition memory depends on the installed option:

  • M9709A-M10: 32 MB/Ch (33,554,432 bytes)
  • M9709A-M40: 128 MB/Ch (134,217,728 bytes)
  • M9709A-M16: 512 MB/Ch (536,870,912 bytes)

 

Sample Rate:

M9709A has an internal sample rate of 1 GS/s.

 

Can be increased or decreased via an external clock:

  • Sample Rate = External Clock Frequency / 4
  • Min Clock = 3.6 GHz; Max Clock = 4.4 GHz

 

Cannot be decreased via binary decimation.

 

Bytes Per Sample:

ADC resolution is 8 bits; every sample requires 1 byte.

 

Examples: M9709A

  • Maximum memory, no external clock
  • Maximum memory, minimum external clock

 

Memory/Channel
(Bytes)

Ext. Clock
(Hz)

Decimation

Sample Rate (Sa/s)

Bytes/
Sample

Time (Secs)

536,870,912

N/A

N/A

1,000,000,000

1

0.53687091

536,870,912

3,600,000,000

N/A

900,000,000

1

0.59652324

 

 

M9710A

 

Maximum acquisition time is calculated as:

Time = (Memory Bits Per Channel) / (Sample Rate * Bits Per Sample)

 

Memory Bits Per Channel:

Acquisition memory depends on the installed option:

  • M9710A-M05: 128 MB/Ch (1,073,741,824 bits)
  • M9710A-M08: 2048 MB/Ch (17,179,869,184 bits)

 

Sample Rate:

M9710A has an internal sample rate of 5 GS/s.

.

Cannot be changed via an external clock.

 

Can be decreased via binary decimation:

  • Decimated Sample Rate = Current Sample Rate / 2n
  • n = integer in the range 1 to 5

 

Bits Per Sample:

ADC resolution is 10 bits; data is packed in this way, so every sample requires 10 bits.

 

Examples: M9710A

  • Maximum memory, no binary decimation
  • Maximum memory, 25 binary decimation

 

Memory/Channel
(Bits)

Ext. Clock
(Hz)

Decimation

Sample Rate
(Sa/s)

Bits/
Sample

Time (Secs)

17,179,869,184

N/A

N/A

5,000,000,000

10

0.34359738

17,179,869,184

N/A

32

156,250,000

10

10.99511628

Outcomes