Title		Author	Latest activity	Views
	10 New Features in ADS 2017 for Signal and Power Integrity Engineers	annamccowan	October 4, 2017 7:35:44 AM by annamccowan	402	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #6: Unintentional Visit to Frequency Domain	Tim Wang Lee	August 15, 2017 1:58:34 PM by Tim Wang Lee	265	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Practical Approach for Signal Integrity Analysis of High Data Rate Channels	kaelly_farnham	August 3, 2017 11:55:35 AM by kaelly_farnham	134	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #5: Demystify Ultra-low Impedance Measurement	Tim Wang Lee	July 31, 2017 3:03:57 PM by Tim Wang Lee	230	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #4: Your Channel, PRBS and the Eye	Tim Wang Lee	July 12, 2017 10:23:23 AM by Tim Wang Lee	472	Show 1 Likes1	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #3.5: Convolution Workspace	Tim Wang Lee	June 28, 2017 2:02:29 PM by Tim Wang Lee	249	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #3: Convolution and Single Pulse Response	Tim Wang Lee	June 22, 2017 4:51:38 PM by Tim Wang Lee	302	Show 1 Likes1	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #2.5 The Arrival Time Inconsistency	Tim Wang Lee	June 14, 2017 6:46:15 PM by Tim Wang Lee	170	Show 0 Likes0	Show 0 Bookmarks0	1 Replies1
	Tim's Blackboard #2: The Dirac Delta Misnomer	Tim Wang Lee	June 8, 2017 5:21:39 PM by Tim Wang Lee	764	Show 4 Likes4	Show 0 Bookmarks0	3 Replies3
	Tim's Blackboard #1.5: the Blink of an Eye	Tim Wang Lee	June 7, 2017 2:32:58 PM by Tim Wang Lee	133	Show 1 Likes1	Show 0 Bookmarks0	0 Replies0
	Tim’s Blackboard #1: The Melting Trace Paradox	Tim Wang Lee	May 24, 2017 3:25:36 PM by Tim Wang Lee	1142	Show 4 Likes4	Show 0 Bookmarks0	0 Replies0
	Have you run into cases where you could not find agreement between your pre-fabrication measurements and post-fabrication lab measurements?	KeysightEEsofEDA	May 15, 2017 9:58:39 AM by KeysightEEsofEDA	199	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	New Approach for Estimating Accurate Statistical-Based DDR4 Margin	KeysightEEsofEDA	April 11, 2017 2:29:55 PM by KeysightEEsofEDA	176	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Looking For A Way To Ensure High Signal Quality In PCIe Gen3 Serial Channels?	kaelly_farnham	March 23, 2017 9:00:08 AM by kaelly_farnham	310	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Keysight DesignCon 2017 Proceedings Are Now Available	KeysightEEsofEDA	February 14, 2017 4:59:56 PM by KeysightEEsofEDA	271	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	DesignCon Wrap-Up: What was hot for design engineers?	kaelly_farnham	February 10, 2017 12:34:00 PM by kaelly_farnham	210	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	8 Steps to a Successful DDR4 Design	kaelly_farnham	February 8, 2017 10:28:37 AM by kaelly_farnham	2735	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Register for Keysight's Latest Tutorial in Signal Integrity Webcast	KeysightEEsofEDA	February 8, 2017 10:24:47 AM by KeysightEEsofEDA	280	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	When SPICE Alone No Longer Works	kaelly_farnham	January 6, 2017 4:30:36 PM by kaelly_farnham	473	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0
	Using S-Parameter Files for Your Parts Is Easier Than You Thought	kaelly_farnham	December 15, 2016 10:04:05 AM by kaelly_farnham	1069	Show 0 Likes0	Show 0 Bookmarks0	0 Replies0