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20 Posts authored by: kaelly_farnham Employee

What is PathWave?

Posted by kaelly_farnham Employee Feb 14, 2018

PathWave is the new design and test software platform from Keysight Technologies. It combines design software, instrument control, and application-specific test software in an open development environment.


PathWave was the big news that Keysight unveiled at DesignCon.


PathWave at DesignConPathWave design and test software platform

PathWave signs were all over the DesignCon floor and meeting rooms. PathWave is an open, scalable, and predictive software platform that integrates hardware and software at every stage in the product development workflow. The PathWave software platform provides you with flexible and immediate access to the design and test tools you need, when you need them. 


Kaelly delivers flash seminar at DesignCon


At the show, I delivered a Flash Seminar about PathWave that was standing room only. Customers were very excited to hear how this new platform will affect them. It will help all engineers who work in design and test save time by connecting and integrating their workflows.


How does PathWave save me time? This was the most common question I got from engineers at the show.


The PathWave platform is built on a software framework that will connect all software and hardware in design, test, measurement, and analysis. On top of the framework, PathWave offers plug-ins and applications, enabling engineers to customize the environment for their specific tasks. It’s the customization combined with the interoperability provided by the common framework that allows for the most time savings. Below is an example.



PathWave Semiconductor Manufacturer Example

PathWave will connect and integrate the entire design and test workflow as shown in this example of a test setup for a semiconductor manufacturer.


PathWave can be customized for many applications, and above is just one example of a semiconductor manufacturer who needs to save test time because they are missing production targets. This customer struggled because they had a growing number of test parameters, were spending too much money on separate software test modules, and had a complex architecture that wasn’t easy to develop in, visualize data flows, or debug.  


With Keysight PathWave, their entire workflow will be connected and integrated with one single platform.  If desired, they’ll automatically get updates for all new releases of the software. They can save even more test time by pushing all the computations to the cloud or a local cloud. They’ll be able to connect to 3rd party hardware, so they can connect to existing equipment they already have. They can choose a software environment that includes a lightweight sequencer, plugin templates, package manager as well as development GUI, results and timing analyzers for best test team collaboration and efficiencies.  They can rely on consistent measurements from early validation to final manufacturing. 


And with Analytics as a big part of PathWave, they will be able to gather, store, and perform analytics on their test equipment and manufacturing data, improving productivity and asset utilization with the built-in predictive algorithms.


This is just one example of how PathWave is saving engineers time. For more information, check out PathWave online or contact Keysight.

Many of you know Matt Ozalas, RF Design Engineer at Keysight Technologies, and his infamous YouTube video series, How to Design an RF Power Amplifier. I got a chance to talk to him about what he’s most excited about in the latest ADS release.

Matt Ozalas, RF Design Engineer at Keysight Technologies


Kaelly: I heard ADS 2017 is being called the “3D release”. What 3D capabilities are you excited for?


Matt: It’s 2017, we’ve got hoverboards and self-driving cars -- we should be designing in 3D by now, right?  Besides the “wow” factor, some tasks are really useful to do in 3D.  I think a lot of designers will feel the same way after trying the new capabilities in ADS 2017 out.  In ADS 2017, those 3D capabilities span design, simulation, and visualization.   So, physical design becomes more realistic early on, the simulation is easier to set up, the results are more accurate, and the analysis becomes more meaningful. 

 3D layout, ADS 2017

In ADS 2017, you can design a layout in three dimensions. You can route a trace or stitch a VIA more precisely in a dense module or chip, and you can select complex structures much more easily in 3D.  This might seem trivial but we’ve all been in that spot where a VIA gets missed or the routing goes to the wrong layer and that causes big problems down the line. Designing in 3D prevents these mistakes from the outset.  The 3D selection also helps if you’re trying to do an EM simulation, getting all the right structures selected is not always easy.  You can even thermally simulate multiple technologies at the same time, like a chip stacked on a substrate.  Let’s face it, no one can afford to overlook these things in the design process anymore, mistakes cost too much and reliability problems are too critical to leave to chance.  Just ask those people making hoverboards.

 RFIC layout, ADS 2017

Kaelly: Designers are always looking for ways to save time. Is ADS 2017 faster than its previous release?


Matt: Yes, let’s look at EM simulation for example.  The Momentum 3D planar EM simulator now uses multi-threading for substrate calculations in ADS 2017.  What does that mean?  Well, typically substrate calculations only use one processor, but for example, your Windows machine probably has four processors.   In ADS 2017, Momentum farms those calculations out to the different processors and so on that Windows machine, you will see a 4x speed improvement in the substrate calculation.   By the way, in Momentum, the substrate calculation is usually the most time-consuming piece.  Now, what about 3D Finite Element Method (FEM) Simulation?  Well, in ADS 2017, this 3D engine has a turbo mode which distributes the simulation frequencies to different processors, and that of course, speeds up the simulation time dramatically.   

 FEM in ADS 2017, finite element method

Kaelly: I know there are many usability improvements in ADS 2017. Which ones are most exciting to you?


Matt: The way I look at it, no matter how good a capability is, if it isn’t easy to use, I probably won’t use it.  So 3DEM simulation is faster, right?  Great, but what about getting your design into that EM engine?  If that takes too long, all the speed improvement is less meaningful.   In ADS 2017, we looked closely at the EM setup process, like what steps designers take before they run an EM simulation.  They set up a substrate, then perhaps if they want to analyze a sub design, they’ll cut that part out, remove unwanted metal, add ports, go play around with some EM settings, and finally click run.   A lot of steps. 

3D EM in ADS 2017


In ADS 2017, you will find that every one of those steps is easier.  The substrate editor has a table definition feature which enables you to easily create and modify highly complicated substrates with lots of layers.  A grouping capability allows you to much more easily group items you want to be modeled. There are even features that allow you to more easily place multiple ports and pins, and assemble and define ports. Separately, these features might not seem all that exciting, but put them together and the result is undeniable: fast and simple EM simulation setup.


Anyone who has ever used the ADS Electro-Thermal simulator knows that defining a substrate involves a text-based file, but not anymore. With ADS 2017, you can accomplish that task using the substrate editor. Just imagine how much easier it will be to visualize your thermal stackup using the substrate editor, rather than writing it into a cryptic text file.


Another great new feature in ADS 2017 is its multi-technology support (e.g., Chip on Package). In the past, if you had a chip that went into a board or module, you then had to simulate those two technologies. You could do it, for sure, with the ADS Electro-Thermal simulator, but it required a 3-page procedure and was impossibly difficult. With ADS 2017, that simulation of multiple technologies just works.


Kaelly: What’s the ADS Python Data Link that I keep hearing about?


Matt: I have been using this capability for all kinds of neat things. This is what I’m most excited about in ADS 2017. In essence, you can take your ADS simulation result and run it through a Python script by just using an equation in data display. The ADS data goes into Python, the script gets run, and the results come back to ADS in one step.  It’s like hooking a rocket engine onto ADS Data Display – and the best part is you never have to leave the simulation environment.  The possibilities are endless: 3D plotting, instrument connectivity, loadpull contours from measured data, all that stuff becomes easy to do, and you don’t even need to know Python to take advantage of it because the scripts already exist and they just run in the background.  The best application I’ve seen of this feature so far is plotting ADS simulation data on a cylindrical 3D Smith Chart, called the “Smith Tube”.  Look up the Smith Tube on IEEE Explore, it is so cool.  It will change the way you think about circuit design – seriously!

 ADS 2017 Data Link with Python

Kaelly: Thanks Matt! I’ll have to check that out.


If you want specific information on any of the features Matt mentions, and some that he didn’t, check out the ADS 2017 release webpage.


free trial of ADS 2017

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Working with data tables is a basic skill every engineer learns early on in their career. When organized properly, tables can summarize a great deal of device data into a helpful information format, and that makes them extremely useful. A 1-page data table can pack as much punch as a thirty-page report that’s full of curves. The table significantly minimizes the time it takes engineers to find the information they're after, while also minimizing paper waste and saving trees!


But not every engineer wants their information displayed in the same tabular format. How the tables are created, organized and filled may differ from one engineer or application to another and that’s why the ability to customize tables is so critical. Doing so, allows engineers to derive the specific information that is so critical to optimizing their design. Unfortunately, generating tables and customizing them to meet specific needs is not always a straightforward task. And that can translate into wasted design time, added cost and slower time to market.


For those engineers wanting to quickly and easily customize tables, the answer comes in the form of Keysight Technologies’ Model Quality Assurance (MQA) solution. MQA is a well known, automated SPICE model validation software that allows engineers to check and analyze SPICE model libraries, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. MQA 2017 extends these capabilities by introducing the Python Report Formatting System (PyRFS) module, which allows engineers to customize tables—either generate new tables or update existing tables—in .csv and .xlsx file formats.


PyRFS is simple enough to generate all sorts of tables quickly, with plenty of options to customize those tables in a flexible and scalable way. For engineers using MQA, that means the ability to sort, filter, formulate, format, and layout data in many different ways. It also enables them to query and have fine control over MQA project results.


And, because it’s Python based, engineers can even feel free to blend in their own favorite Python stuff. For you personally, having access to this functionality promises to cut your design time and speed time to market.


But, how do you leverage this module? To do that, I’ll walk you through a simple, yet complete flow for creating a .xlsx file using the table in Figure 1 as an example. The table filters and sorts W/L/T for certain device targets (Idsat).

excel example table for MQA module

Figure 1. Example table.

The example table comes from the QA result of one MQA rule “Model Scalability -> Check Idsat vs L,” where there are Idsat curves from 3 temperatures and different W and L. The demo project to reproduce this example can be found as $MQAHOME/kefrfs/python/demo/data/. The first few lines of the code for generating this table are shown in Figure 2.

python code for MQA module

Figure 2. Initial code for creating the table in Figure 1.


In Figure 2, line 1 and 2 import necessary Python modules; “os” is Python’s native module for the operation system, and “pyrfs” is the module that comes with MQA 2017. Line 4 gets the current python file’s directory, while line 5 locates the example MQA project folder’s path. Line 6 prepares the option called “config,” which specifies that the project’s path is to be fed into line 7. Line 7 then creates a data provider “dp”, and gives it access to all of the information of the specified project for you to query.


On line 9, the “dp.query()” function is called by specifying “rule_group,” “rule,” and “check” as arguments. The values of these arguments are the folder names, respectively. The “dp” object has been narrowed down to information only from this node. Lines 10 – 12 are designed to get W/L/T as conditions, while line 13 gets Idsat as a target.


Figure 3 shows the next few lines of code. On line 15, a “table” is created by calling “rfs.ReportTable()” and giving “example_idsat_table” as its name. At the end, a file with this name is created.

 additional lines of code for MQA module

Figure 3. Additional lines of code need to generate the table in Figure 1.


Line 16 defines a RightLayout and associates it with the “table.” A Layout is how we fill up the table. RightLayout means PyRFS will automatically fill the table from left to right, starting from the top-left cell “A1” by default, and growing rows and columns as necessary so that you don’t need to worry about cell indices.


Line 17 adds W, L into the table with a few options to make them appear in one column with a certain format, ascending, and filtered by L=Lmin. Line 24 adds Idsat into the table, and repeats it in 3 columns because it is dependent on the 3 temperatures to be added in line 25. Once these constraints are well defined, lines 30 and 31 fill up and save the table, respectively.


From this simple example, it’s easy to see how useful the PyRFS module is and how helpful it can be in automating your table generation tasks. For more information on the PyRFS module functionality and step-by-step examples of how it can be used, refer to the “PyRFS Function List” at the end of the blog and check out the online PyRFS Tutorial at:


PyRFS Function List

The MQA 2017 PyRFS is a powerful Python module for easy, yet fully customizable table generation and reporting. Below is a summary of the functions that PyRFS provides:

  • Automatic extraction of constraints (data collections) from MQA result directories
  • Generation of tables and ability to save them as Microsoft Excel .xlsx files or .csv files on Linux and Windows platforms
  • Support for updating .xlsx files under Windows.
  • Support for sorting and filtering per user specification
  • Support for customized formatting of constraints in tables
  • Support for formulas calculated from other constraints in tables
  • Ability to divide data into different tables, sheets, or files per user specified conditions


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Understanding the impact thermal effects can have on your circuit design is critical to being able to adequately account for them during the design process. It’s also essential to designing your circuit in an efficient way. But that’s easier said than done. A recently released video from Wolfspeed may offer you some much-needed help.


The solution involves using the Wolfspeed MMIC process design kit (PDK) that works in Keysight EEsof EDA’s Advanced Design System (ADS) software. A key feature of the Wolfspeed ADS MMIC PDK is that it’s configured to work with the ADS Electro-Thermal Simulator to co-simulate electrical and thermal performance. The feature is a powerful tool that allows you to account for the significant thermal effects that can occur when using a high-power density technology like GaN.

To demonstrate this capability, the video details the example of a simple, single-pole tuned 10-GHz power amplifier. The design uses a 1.2-mm FET and its goal is to put out about 5 watts at temperature.

Layout of the single-pole tuned 10-GHz power amplifier, designed using only elements from the PDK itself.

The layout of the single-pole tuned 10-GHz power amplifier, designed using only elements from the PDK itself.


 Schematic of the electro-thermal simulation of the single-pole tuned 10-GHz power amplifier.

Schematic of the electro-thermal simulation of the single-pole tuned 10-GHz power amplifier.


Data display of the simulation of the single-pole tuned 10-GHz power amplifier from Keysight ADS software.

Data display of the simulation of the single-pole tuned 10-GHz power amplifier from Keysight ADS software.


With the ADS Electro-Thermal Simulator, Wolfspeed was able to get an accurate, “temperature aware” IC simulation result for the PA using device temperatures that took into account both thermal coupling and the thermal characteristics of the package.

Electro-thermal simulation of the single-pole tuned 10-GHz power amplifier. Peak is at 180 degrees.

 Electro-thermal simulation of the single-pole tuned 10-GHz power amplifier. The peak is at 180 degrees.


3D view of the electro-thermal simulation of the single-pole tuned 10-GHz power amplifier.

3D view of the electro-thermal simulation of the single-pole tuned 10-GHz power amplifier.


For specific details on how the ADS Electro-Thermal simulator was used in the design of the 10-GHz PA, watch the video below.


More information on the ADS Electro-Thermal Simulator is available here.


free trial, ADS, Keysight

Accurate and efficient modeling is critical to successful design, especially when it comes to the Static Random Access Memory (SRAM) cell, the minimum geometry devices in integrated circuit technology. Modeling such circuits has grown increasingly complex with the advent of nanometer scale process geometries. That’s because increasing process variation makes model stability more challenging.


The latest release of Keysight Technologies’ Model Builder Program (MBP) 2017 now features a SRAM cell model generation package that’s designed to address this challenge head on, by enabling engineers to extract transistor-level and memory-cell models in one MBP session. The user can easily simulate cell-level figures-of-merit, tune model parameters and even compare two memory cell models (Figure 1).

 Comparison of two SRAM cell models, MPB 2017


Figure 1. With MBP 2017, users can easily compare SRAM cell models.


According to Roberto Tinti, Keysight’s Device Modeling Planning Manager, the extraction package came about as a result of a collaboration with a major customer. “Working together we developed a solution that not only reduces modeling iteration but cuts the design cycle as well. It promises to bring many benefits to both existing and future MBP customers.”


Additional enhancements in MBP 2017 include:

  • An enhanced statistical model extraction flow and updated application examples
  • Enhanced extraction flows for BSIM3v3, BSIM4, and BSIM-CMG
  • Updates to the following models: BSIM-CMG 110.0, BSIM-CMG 109.0, BSIM-IMG 102.8, BSIM-IMG 102.7, HiSIM2 2.9.0, HiSIM_HV 2.3.2, HiSIM_HV 2.3.1, HiSIM_HV 2.3.0, EKV 302.00


scripts-based model extraction flow. MBP 2017

Figure 2. Available in MBP 2017 is an updated scripts-based model extraction flow. 


Keysight has also released a new version of its Model Quality Assurance (MQA) 2017 software with enhancements designed to improve modeling efficiency and model quality. MQA 2017 contains a new internal SPICE3 engine that allows users to run quick simulation and quality assurance (QA). It supports the latest compact model versions. Python scripts are also now supported, enabling generation of user-defined Excel tables based on exciting QA results.


"The advanced effects and parasitics in new devices make device modeling more complicated than ever,” said MA Long, Device Modeling Product Manager with Keysight. “With the new internal engine, users can run model quality checks during parameter extraction and uncover potential risks in the early design stage. Support for Python scripts provides the user even more flexibility and functionality in generating tables over the existing TCL and Perl solutions offered."

 compare table generation with python script, MQA 2017

 Figure 3. N/P compare table generation with Python Script as provided by MQA 2017. 


Other enhancements in MQA 2017 include support for Spectre native aging simulation, SmartSpice version 4.26.7.R and Microsoft Office 2016. Unlike traditional manual scripting methods, MQA enables users to check their SPICE models, compare models and generate QA reports in a complete and efficient way.


MBP and MQA are Keysight’s industry-leading device modeling and characterization products. MQA is the industry standard for SPICE model acceptance and sign off, and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses. Information on MBP 2017 and MQA 2017, is available at and, respectively. To apply for a free software trial, go to and


 free trial


There’s a saying around the industry that goes something like “everyone trusts a measurement, except the person who made it, and no one trusts a simulation, except for the person who did the simulation”.  Either way, both have lots of nuances which can impact the end result. Comparing simulation to measurement can be a very difficult task. 


For example, consider the case of a PAM-4 signal through a channel.  By transmitting 2 bits per clock cycle, PAM-4 (Pulse-Amplitude-Modulation, 4 amplitude levels) offers high data rate transmission (56 Gb/s), but there are challenges to implementation; with 4 levels, the traditional eye diagram splits into 3 eyes, meaning less noise and distortion can be tolerated in the channel. 

PAM-4 waveform

Figure 1. PAM-4 waveform.


Because the signal in PAM-4 is more sensitive, an accurate simulation of the channel is essential.  A channel simulation takes the modulated signal and sends it through a physical link (like a cable) to see how the clean signal gets distorted by the channel.   Given the straightforward setup, it may seem simple to correlate simulation to measurement – after all, we can potentially use the same waveform in both simulation and measurement (using an AWG), or measure the S-parameters of the channel directly and use that data in the simulation.  The results should easily correlate, right?  Unfortunately, there are still nuances that can lead to different results. 

Channel measurement setup

Figure 2. Channel measurement setup.


In an eye diagram measurement on an oscilloscope, the signal will likely be preprocessed prior to measurement.  For example, the waveform will be filtered or noise will be injected into the raw waveform.  Modern instruments contain all kinds of tools and functions for data analysis – and these are not always easy to recreate elsewhere (sometimes they’re even proprietary!).


There are also functions in simulation tools that generate eye diagrams– but we wonder what processing is being done in the background?  It’s not always clear.  We could have the exact same signal on the scope and in the simulation, and due to different data processing techniques, get different eye diagrams!  Yikes!

Measured Eye Diagram on Keysight DCA-X 86100D oscilloscope vs. Simulated Eye Diagram in Keysight ADS

Figure 3. Measured eye diagram on Keysight DCA-X 86100D oscilloscope compared to a simulated eye diagram in Keysight ADS.


To eliminate uncertainty, its best to process both waveforms in the same place with the same functions.  But getting measurement data into the simulation environment can be tricky, and getting simulated data onto an oscilloscope could be even trickier.


Wouldn’t it be great if you could just talk to the instrument directly from the simulation tool?  That way, you could configure the instrument, load a waveform, make some measurements, and maybe even return data back to simulation – all without ever leaving your desk.    


Well, now you can!  Using a link between Keysight ADS and Python, it’s possible to transfer data between the simulation and measurement environments, and even control the instrument directly using SCPI commands.  And the great thing is, you don’t even need to know Python to do basic instrument IO.


ADS functions are now available which invoke Python behind the scenes, allowing you to send SCPI commands from ADS to configure a measurement or capture a waveform trace.  All you need to do is load the ADS functions, set up your libraries ( and you’ll be controlling instruments in no time.  The figure below shows how it’s possible to capture a measured PAM-4 waveform directly into ADS with a few simple SCPI commands.

Capturing measured PAM-4 waveform into ADS using SCPI commands

Figure 4. Capturing measured PAM-4 waveform into ADS using SCPI commands.


In the case of the PAM-4 signal mentioned at the beginning, it might be better to process the simulated waveform on the measurement test equipment because the Keysight DCA-X 86100D oscilloscope has lots of built in functionality.  In this case, we can use a Python script to do the heavy lifting: loading the simulation data into the DCA-X 86100D, configuring the scope, processing the eye statistics, and returning the levels back to ADS.  At the same time, you could also measure the physical channel for direct comparison with simulation, using the exact same processing algorithms.  After the Python script has been developed, you can do this all in one step using the ADS Data Link to call the script, transfer the data and receive results back.    

Calling a Python script from ADS to load simulated channel output waveform and compare it directly with the measured waveform.  ADS calls the script and the corresponding PAM-4 levels for both simulation and measurement are returned to ADS.

Figure 5. Calling a Python script from ADS to load simulated channel output waveform and compare it directly with the measured waveform.  ADS calls the script and the corresponding PAM-4 levels for both simulation and measurement are returned to ADS.


For more information watch these videos on YouTube:

  1. Video: ADS Data Link Basics (Part 1 of 3)
  2. Video: Advanced Plotting Using the ADS Data Link (Part 2 of 3)
  3. Video: Instrument Connectivity (Part 3 of 3)

Registered users can view the following application notes in the Keysight EEsof EDA Knowledge Center (register here):

  1. App Note: ADS Data Link Basics
  2. App Note: Advanced Plotting
  3. App Note: Instrument Connectivity


Apply today for your free 30-day full-version trial of Keysight ADS.

FREE Evaluation of ADS | Keysight EEsof EDA 

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If you’re looking for help designing a broadband Power Amplifier (PA), the 3D Smith Chart may be just the answer for you. 3D Smith Charts can be easily generated from Keysight’s Advanced Design System (ADS) software using Python scripts. You don’t even need to know Python. A Data Link with Python in ADS provides a simple way for you to call preprogrammed Python scripts, complete with bi-directional data transfer.


The Cylindrical 3D Smith Chart (also called the "Smith Tube") was pioneered by a team at Baylor University led by Dr. Baylis and presented in a landmark IEEE WAMICON paper in 2014 that introduced the "Smith Tube" in the literature for the very first time (see more references at the end). 


Here are 5 ways a 3D Smith Chart can help you design a broadband PA:


1. It gives you a unique perspective and fast insight into resonance.

LC impedance matching network topology, S22 response

 Figure 1.  This LC impedance matching network topology may at first seem simple to analyze.

s22 response, smith chart


Figure 2. It’s not always obvious, why, for example, a particular resonant inflection occurs in the S22 response such as the one shown at 1.52 GHz.


While an LC impedance matching network for a PA design may seem simple to analyze, understanding why a resonance inflection occurs is not always easy (Figure 1 and 2). If you can get to the root of the resonance, you can exploit it to build a broadband match. A 3D Smith Chart allows you to do just that. By plotting the impedance shift of each individual matching component at each frequency, you can find the cause of a resonance and determine what adjustments are needed to mitigate its effects (Figure 3).

3D Smith Chart, Smith Chart

 3D Smith Chart, Smith Chart3D Smith Chart, Smith Chart
















Figure 3. From these 3D plots, now we can see the resonance around 1.5 GHz occurs due to the impedance from C3, which is “spinning” around the impedance set by the rest of the network.


2. You can create a solid 3D surface. 

3D Smith Chart, Smith Chart, EVM contours, EVM surface3D Smith Chart, Smith Chart, EVM contours, EVM surface














Figure 4. An example EVM surface represented by a set of load-pull contours is shown. By viewing the entire surface in this format, some interesting things stand out that aren’t immediately obvious from the contours.


In PA design, load pull is typically used to sweep a transistor's load and plot contours of constant performance (e.g., output power). Load-pull contours are a flat representation of a 3D surface. Sometimes they are easy to interpret and design with, but using them to interpret the surface topology of complex structures can be challenging. Plotting the entire surface as a 3D solid structure can be very insightful in some instances, for example, finding the minimum EVM region of a PA under a modulated input signal (Figure 4).


 3. You can extend contours to the third dimension.

3D Smith Chart, Smith Chart

Figure 5. A plot of load-pull contours in 3D (with the third dimension being frequency) is shown. 


Suppose you’re trying to design an amplifier to deliver high output power over a broad bandwidth. Typically, this would be done by performing load-pull simulations at several frequencies and then trying to build a matching network to hit the correct loads to deliver the power required for each individual frequency. Using a 1D Smith Chart, this would be a long, difficult process, resulting in so much clutter on the plot that you would likely be unable to make sense of the results. Typically, a designer can only visualize one contour or single frequency set of contours at a time. Plotting the same contours on a 3D Smith Chart “spreads out” the contours and allows you to visualize more information at once (Figure 5).


 4. You can create a surface from cross-sectional data.

 3D Smith Chart, Smith Chart

Figure 6. Another way to visualize the frequency dependent power contours in Figure 5 is to create a solid surface by connecting the contours together in the Z dimension.


With a 3D Smith Chart you can create a solid “triangulated” surface by connecting the contours together in the Z-dimension. This provides you yet another way to visualize the contour data in 3 dimensions. In some cases, contour surfaces are easier to understand than repeated individual contours.


 5. You can plot your 3D matching network and frequency-dependent load-pull contours on the same 3D Smith Chart.

3D Smith Chart, Keysight ADS, ADS Python Data Link Basics3D Smith Chart, Smith Chart
















Figure 7.  The 3D matching network and the frequency-dependent load pull contours are plotted on the same 3D Smith Chart.


By plotting this data together, it’s intuitive to adjust the matching network component values so that the impedance "threads the needle" though the Pout power contour level across the frequency band. An interactive highlight marker in ADS helps you gain insight into what adjustments are needed.


 4 ways to boost simulation data processing using python          Matt Ozalas

These 5 applications of the 3D Smith Chart came from my friend, Matt Ozalas, RF Design Expert. Hear from him yourself in his May 4th, 2017 webcast, Four Ways to Boost Simulation Data Processing Using Python.

 How to Design a Power Amplifier: The Basics

 You might recognize him from his YouTube Series, How to Design a Power Amplifier: The Basics.


 free trial, ADS, Keysight

Apply today for your free 30-day full version trial of Keysight ADS. 


 For more information, see the following IEEE papers:

1. Joseph Barkate ; Matthew Fellows ; Jennifer Barlow ; Charles Baylis ; Robert J. Marks.  "The Power Smith Tube: Joint optimization of power amplifier input power and load impedance for power-added efficiency and adjacent-channel power ratio". IEEE Wamicon, 2015.

2. Matthew Fellows ; Matthew Flachsbart ; Jennifer Barlow ; Joseph Barkate ; Charles Baylis ; Lawrence Cohen ; Robert J. Marks.  "Optimization of power-amplifier load impedance and waveform bandwidth for real-time reconfigurable radar".  IEEE Transactions on Aerospace and Electronic Systems ( Volume: 51, Issue: 3, July 2015 ).

3. Matthew Fellows, Sarvin Rezayat,Jennifer Barlow, Joseph Barkate, Alexander Tsatsoulas,Charles Baylis,Lawrence Cohen. "The bias smith tube: Simultaneous optimization of bias voltage and load impedance in power amplifier design." Radio and Wireless Symposium (RWS), IEEE. 24-27 Jan. 2016.

4. Charles Baylis; Matthew Fellows; Matthew Flachsbart; Jennifer Barlow; Joseph Barkate; Robert J. Marks.  "Enabling the Internet of Things: Reconfigurable power amplifier techniques using intelligent algorithms and the smith tube".  2014 IEEE Dallas Circuits and Systems Conference (DCAS).


Go straight to the Knowledge Center article (login required): How to Create your own 3D Smith Chart Plots


Engineers surround themselves with the best tools they can find. For the RF engineer, a new tool discussed in the literature recently is the Cylindrical 3D Smith Chart (also called the “Smith Tube”).  This 3D version of the classical Smith Chart allows engineers to explore data in new and interesting ways. It was pioneered by a team at Baylor University led by Dr. Baylis and presented in a landmark IEEE WAMICON paper in 2014 that introduced the "Smith Tube" in the literature for the very first time (see more references at the end). 


The Smith Chart was developed in the 1930’s as a graphical way to transform complex impedances to reflection coefficients.  For an unassuming diagram based on slide rules, the Smith Chart is still enormously relevant in the digital age; in fact, most engineers try to fit so much data into this small circle that we end up with more lines, arcs, and circles than we can ever interpret.  With access to so much data these days, things can get awfully cluttered.  Now, it’s possible to make sense out of more data by adding a third dimension to the classical Smith Chart plot.  For example, on the classic Smith Chart, you can visualize how impedance changes versus frequency.  On the 3D Smith Chart, you can understand how impedance changes versus frequency AND voltage…or gain…or input power, or anything you can imagine!   


To create a 3D Smith Chart, simply take a standard Smith Chart and stack it on an arbitrary Z-axis (Figure 1). The Z-axis can take on any value or scale you desire, such as frequency, power, or transmission line length. The composite plot is then just a stacked set of Smith Charts with each "slice" representing a single classical Smith Chart for a given Z value. 

 3D Smith Chart, Smith Chart

Figure 1. The 3D Smith Chart is analogous to generating a plot in Cylindrical Coordinates, where a cross-sectional plane is represented in polar form by (r,Ɵ) , and the Z-axis is specified in the standard Cartesian Coordinate system.


3D Smith Charts can be easily created using a Python library which can be set up to plug directly into Keysight ADS, which allows you to access this capability to plot and analyze simulation or measurement data.


How to Set Up Your Own 3D Smith Chart


The first step is to set up the ADS Data Link with Python, which provides a simple way to call a Python script from ADS, complete with bi-directional data transfer. Find out how in the video below. Registered users can also view the application note, ADS Data Link with Python

ADS Data Link Basics (Part 1 of 3) - YouTube 


To use the ADS Data Link with Python, you must first install Python Anaconda (available at no charge), and then load the functions into ADS. The ADS and Python functions needed for this setup are available in the workspaces (for registered users). A Data Display with interactive step-by-step instructions is included in the workspace and will walk you through the setup for your particular machine (Figure 2).  

 3D Smith Chart, Keysight ADS, ADS Python Data Link Basics

Figure 2. For most ADS users, this simple data display page should be all that’s needed for setup.


Following setup, you can call Python scripts directly from ADS using previously loaded functions. They can be invoked either from Data Display or from Schematic through a MeasEqn component. To execute a Python script and return what the script prints to the command line, use the following ADS equation:

Eqn Rtn=call_python_script(C"\\PythonScripts","")

Since Python scripts are typically used to process and/or plot data generated from an ADS simulation, you will also need to pass ADS data into Python and then receive data back into ADS from Python. This can be done using the following equation:


ADS_RtnData=call_python_script_IO(PATH to Directory of Python Script, Python Script Name, Data1, Data2, Data3...,DataN)


The above function exports data from ADS into Python, runs the specified Python script (which can access the data), and automatically exports data back to ADS using the Python script—all in one step. Using this function along with a predefined Python script, you can generate a 3D Smith Chart from ADS and plot simulation data on it. The Python scripts used to generate the 3D Smith Chart are provided in the workspace folder ./Smith_3D_wrk/data/Python, provided for registered users. 


Similar 3D Smith Chart plots can be generated from other workspaces. All you have to do is adjust the path string in the function "call_python_script_IO()" to point to the location of the Python folder that has the 3D Smith Chart scripts you are calling.


The above process is ideal if you want to plot points, lines, simple surfaces, and contours using data generated from ADS simulations. If you’re interested in using Python scripting to generate more advanced plots on the 3D Smith Chart; however, then you’ll want to get a better understanding of the Python functions that enable 3D Smith Chart plotting.


Watch this video to see advanced plotting using the ADS Data Python link. Registered users can view the application note, How to Create your own 3D Smith Chart Plots

Advanced Plotting Using the ADS Data Link (Part 2 of 3) - YouTube  


You can see that the 3D Smith Chart offers you unique insights that other standard plotting tools simply cannot, and we've only just begun. Find out so much more in this upcoming live webcast: Four Ways to Boost Simulation Data Processing Using Python.


Four Ways to Boost Simulation Data Processing Using Python


Registered users can view the following resources in the Keysight EEsof EDA Knowledge Center (register here):


Apply today for your free 30-day full-version trial of Keysight ADS. 

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 For more information on the "3D Smith Tube" from the team at Baylor University, see the following IEEE papers:

1. Joseph Barkate ; Matthew Fellows ; Jennifer Barlow ; Charles Baylis ; Robert J. Marks.  "The Power Smith Tube: Joint optimization of power amplifier input power and load impedance for power-added efficiency and adjacent-channel power ratio". IEEE Wamicon, 2015.

2. Matthew Fellows ; Matthew Flachsbart ; Jennifer Barlow ; Joseph Barkate ; Charles Baylis ; Lawrence Cohen ; Robert J. Marks.  "Optimization of power-amplifier load impedance and waveform bandwidth for real-time reconfigurable radar".  IEEE Transactions on Aerospace and Electronic Systems ( Volume: 51, Issue: 3, July 2015 ).

3. Matthew Fellows, Sarvin Rezayat,Jennifer Barlow, Joseph Barkate, Alexander Tsatsoulas,Charles Baylis,Lawrence Cohen. "The bias smith tube: Simultaneous optimization of bias voltage and load impedance in power amplifier design." Radio and Wireless Symposium (RWS), IEEE. 24-27 Jan. 2016.

4. Charles Baylis; Matthew Fellows; Matthew Flachsbart; Jennifer Barlow; Joseph Barkate; Robert J. Marks.  "Enabling the Internet of Things: Reconfigurable power amplifier techniques using intelligent algorithms and the smith tube".  2014 IEEE Dallas Circuits and Systems Conference (DCAS).


PCI Express Gen3 (PCIe Gen3) specifies a high-speed differential I/O interconnect that runs at 8.0 Gbps. It has many benefits, and it also presents a critical challenge. PCIe, using high-speed 8-Gbps serial links, can suffer from a large array of physical phenomena and this can lead to excessive EMI emissions in large systems. Fortunately, there is a way to overcome this challenge and ensure high signal quality in PCIe Gen3 serial channels. The solution involves the use of signal integrity analysis, compliance testing, and a PCIe interface simulation methodology that relies on IBIS-AMI models to account for different channel parameters—all of which can be accomplished using Advanced Design System (ADS) software (Figures 1 and 2).

 SI analysis, PCIe Connector, PCIe Gen3, eye diagram, Keysight ADS

Figure 1. During SI analysis, the PCIe connector, 8-lane data bus and package are simulated using an EM solver. S-parameter data is then extracted and factors like impedance matching and propagation delay are analyzed. Finally, all data is re-combined and a Pseudo-Random Bit Sequence (PRBS) is generated at a bit rate of 8 Gbps. The simulation setup and result of a transient analysis with PRBS random data input for the channel is shown here.


PCIe channel, PCIe 3.0, Keysight ADS

Figure 2. Compliance testing ensures products are interoperable. It validates that the PCIe channel is compliant with the PCIe specification. Shown here is the eye and jitter measurement in ADS on a PCIe 3.0 transmitter transaction bit.


Want to learn more about this approach and what it entails? Check out the article, Ensuring High Signal Quality in PCIe Gen3 Channels, by Keysight Technologies’ Anil Kumar Pandey in the Signal Integrity Journal.  


SIPro, PIPro, free trial


How exactly do you simulate the RF performance of Narrowband IoT (NB-IoT), a standards-based, low-power wide area technology developed to enable a wide range of new IoT devices and services? That’s the question ASTRI— Hong Kong’s Applied Science and Technology Research Institute—faced when it discovered that the RF performance specified in the receiver wideband intermodulation definition for the 3GPP standard might not be accurate.


The issue, as ASTRI saw it, was fairly straightforward. The wideband intermodulation definition for NB-IoT, as defined in 3GPP TS 36.101 (version 13.6.1), originally established the signal power parameter as REFSENS+6dB. But this parameter did not take into account the sensitivity of NB-IoT. In later standardization, the narrowband benefit of NB-IoT was taken into account in the sensitivity definition, with the NB-IoT sensitivity being set to around 7.7 dB lower than that of the enhancements for Machine-Type Communications (eMTC) standard. And that made ASTRI wonder: Is it logical to take signal power into account again in the NB-IoT wideband intermodulation definition?

 3GPP, NB-IoT, wideband

Figure 1. Shown here is the wideband intermodulation definition for NB-IoT, category NB1, from 3GPP TS 36.101 (version 13.6.1).


As an active participant in the 3GPP NB-IoT standardization process, ASTRI knew it had to get to the bottom of this question, but how? The answer lay in the use of the SystemVue electronic design automation (EDA) environment (FREE trial available) to simulate NB-IoT RF performance.


Using the software and its embedded NB-IoT library, ASTRI set up a simulation to study the effect of the NB-IoT receiver wideband intermodulation definition. First, it built a system-level simulation platform for an NB-IoT receiver (Figure 2). The Low Intermediate Frequency (Low-IF) NB-IoT receiver design used for the simulation, with the local oscillator phase noise, nonlinearity and noise figure of each module modeled, is shown in Figure 3. Then, the Bit Error Rate (BER) for the design was measured to evaluate the effect of the receiver’s performance on signal demodulation.

LTE Advanced, NB-IoT, Downlink transmitter, SystemVue, ASTRI

Figure 2. The NB-IoT receiver simulation platform, modeled in Keysight SystemVue.

NB-IoT, receiver simulation, SystemVue, ASTRI

Figure 3. The Low-IF NB-IoT receiver, modeled in Keysight SystemVue.


Figure 4 shows the signal and interferers at the receiver input in simulation. For simplicity, a QPSK signal with 1.4-MHz bandwidth was used as the modulated interferer.


Figure 5 shows an example of the LO phase noise requirement with different signal power definitions in the NB-IoT receiver design. As can be seen by the simulation result, if the input signal is set to REFSENS+6dB, the receiver’s LO phase noise would need to be no worse than the red curve in Figure 5 to achieve a BER of zero. Wideband intermodulation, therefore, becomes the bottleneck for the receiver LO phase noise requirement. Moreover, much more current would be needed to achieve the phase noise requirement, especially for high-frequency bands. And this means that the NB-IoT wideband intermodulation definition would essentially lead to higher power consumption for NB-IoT user equipment; something that runs counter to the low power requirement of most IoT applications.


 NB-IoT, SystemVue, signal and interferers

Figure 4. Signal and interferers at the receiver input.


LO phase noise requirement, 3GPP, SystemVue, NB IoT

Figure 5. An example for the LO phase noise requirement with different signal power definitions.


On the other hand, if the input signal power in the wideband intermodulation definition for NB-IoT is set to REFSENS+12dB, rather than REFSENS+6dB—as it is for LTE  and eMTC in 3GPP TS 36.101 (version 13.6.1)—then the LO phase noise for 1 MHz to approximately 7.5 MHz can be relaxed by 10 dB (shown by the blue curve in Figure 5) to achieve a BER of zero from the simulation. By doing so, wideband intermodulation no longer acts as the bottleneck of the LO phase noise requirement. Instead, it is mainly related to the linearity of the RF front-end, which is in line with the definitions for LTE and eMTC. 


Based on these SystemVue simulation results, ASTRI proposed that the Category NB1 signal power specification shown in Figure 1 be revised from REFSENS+6dB to REFSENS+12dB in 3GPP RAN4 #82 meeting held in Athens, Greece this February. The 3GPP standards body accepted this proposal after in-depth discussion and the parameter will be updated accordingly in the coming version of 3GPP TS 36.101. The revision on the parameter further optimized NB-IoT User Equipment (UE) standard, and will facilitate the implementation of low power NB-IoT terminal chip.


For more information on the value of SystemVue software for baseband and RF simulation go to: For more information on the NB-IoT, go to:


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I just got back from DesignCon 2017, the premier conference for chip, board, and systems design engineers held annually in Santa Clara, CA. This year did not disappoint. With so many design engineers from Silicon Valley and all over the world, you can be sure that the latest technologies were being discussed for high-speed digital designs.  


What was hot?

  • 112 Gbps PAM-4. Speeds are ramping up and 112 Gbps is legit.
  • DuoBinary Signaling. Another modulation format that might just get you more speed.
  • DDR4 & DDR5. Especially with a focus on equalization and more formal statistical simulation methods.
  • Chiphead. He always made time to stop for pictures.

DesignCon, Chiphead

What was not?

  • PAM-8. This higher order modulation suffers from an even further reduced Signal-to-Noise ratio.  Doesn’t look like a prime candidate for the next wave of innovation.    
  • Silicon photonics. Progressively moving ahead, chip-to-chip optical links are closer to being a serious technology contender.  No end to the reign of the electrical backplane for the foreseeable future.        
  • USB Type-C. Interest in USB 3.1 on its own is very last year.  Now the talk turns to the wider adoption of USB Type-C physical layer as a way to bundle USB/Thunderbolt3/DisplayPort signaling.  One connector to rule them all… 
  • The weather. It rained the whole week.

Keysight, software, services, umbrella

My colleague, Heidi Barnes, won DesignCon Engineer of the Year. You might remember her from my previous post, Underwater hockey playing design engineer. It was great to watch her in the Panel Discussion with previous winners, Mike Steinberger (2015) and Eric Bogatin (2016). Heidi was on the DesignCon planning committee and also presented many papers at the show (you can download them here)

Heidi Barnes, DesignCon Engineer of the Year


As for Keysight EEsof EDA, we had a great show. Last year we launched SIPro & PIPro, two new EM analysis solutions, which work inside Keysight ADS to provide transient circuit simulation and channel simulation technologies for analysis of high-speed serial links and memory systems. This year we met with many of our customers who have already adopted SIPro and PIPro, and incorporated it into their flow.

DesignCon, SIPro, PIPro, Keysight EEsof EDA


We just released ADS 2016 Update 1, incorporating new Mesh Domain Optimization (MDO) technology, which reduces simulation time even further, by more than 2x compared to the initial release, for SI and PI analyses.


Looking forward to even more improvements in SIPro & PIPro in 2017.


sipro, pipro, free trial

When SPICE Alone No Longer Works, Channel Simulator Technology May Help


As a designer, chances are you’ve been there. You’re measuring the margin-to-mask for really low bit-error-rates (BER), a task required for high-speed link designs, and the transient simulation (SPICE) you’ve been using no longer seems to work. What are your options? Channel Simulation, as found in Keysight ADS Software, and improved upon in the latest ADS 2016 release, provides a trusted solution.


Before Channel Simulation, the common approach used to simulate a high-speed link design was transient simulation. But, that left designers struggling with questions like: What margin do I have at a BER of 1e-9, 1e-12 or 1e-16?  Transient simulation alone could not deal with these questions because the sheer number of time steps required was beyond practical means.


What margin do I have at a BER of 1e-9, 1e-12 or 1e-16?


The answer to overcoming that hardship lies in being able to compute BER contours with Channel Simulation, a solution built on a strong foundation of technical innovation. Beginning with Dr. Fangyi Rao’s 2006 patent to correct for passivity, while ensuring causality, in bandlimited frequency-domain models, Keysight ADS established itself as the industry-leading Channel Simulator. Using it, you gained access to an accurate solution capable of handling cascades of S-parameter models combined with circuit models in one schematic. In 2009, bit-by-bit channel simulation was released. In 2010, statistical channel simulation was released. In 2011, IBIS-AMI support for channel simulation was introduced. The pace of innovation continues even today, and ADS's channel simulator is widely regarded as the industry standard. 

 IBIS, ADS 2016, Channel Simulator, signal integrity, SPICE

Figure 1. In addition to allowing designers to mix-and-match models, ADS 2016 Channel Simulator now supports IBIS package (.pkg) entries directly, and more extensively than before. It also offers pre-standard support for IBIS v6.1, even before the official IBIS parser is available. Get a free trial of ADS 2016


As the high-speed link designer, you can now freely mix and match models from IBIS, IBIS_AMI and SPICE, as well as generic built-in models (Figure 1). You can even access the Channel Simulator’s own IBIS-AMI Tx and Rx models for PCIe3, USB 3.1 and 100 GbE, which ship with Compliance Test Benches and example workspaces (Figure 2 and 3). Such capabilities are crucial when SPICE alone simply no longer works. 

 channel simulation, M-PHY simulation, NRZ signaling, ADS 2016

Figure 2. ADS 2016 provides a template for MIPI C-PHY, D-PHY, and in this case, MIPI M-PHY simulation. Get a free trial of ADS 2016.


channel simulation, PCIe3, BER contours, equalization, ADS 2016, Compliance Test Bench

Figure 3. ADS 2016 features PCIe3 standard-specific EQ presets, which have been added to the PCIe 3 Compliance Test Bench. Get a free trial of ADS 2016.


For more information on measuring margin-to-mask in high-speed link design when SPICE alone no longer works, check out 8 Ways ADS 2016 Helps You Overcome Signal and Power Integrity Challenges.


ADS Free trial

It’s a common problem. You’ve just downloaded the S-parameter file for a part you’re considering using in your design; say, a high-speed connector for a backplane. Because it has a large number of ports, the first thing you want to do is inspect the quality of the data. Then, you want to use it in your simulation. But, how exactly do you wire it up and which ports do you pair?


You can go the traditional route, which involves opening the data in a text editor. But given the overall complexity and time consuming nature of the design process in general, there has got to be an easier way to deal with this data. And now there is! It’s a feature called the S-Parameter Checker and it’s available in ADS 2016 (FREE trial available here).


With S-Parameter Checker, you can easily view S-parameter file contents without ever having to setup an S-parameter test bench simulation (Figure 1). Instead, you directly plot the individual relations you want to see. You can also see the port names against each pin. The software tells you whether the file is passive or reciprocal, as well as the number of data points in the file and the frequency range it covers.

ADS 2016, S-Parameter Files, Keysight EEsof EDA, S-Parameter Checker

Figure 1. ADS 2016 S-Parameter Checker allows design engineers to easily rename, re-order and reduce the number of ports, enabling a new, more usable S-parameter file.

 Keysight EEsof EDA, ADS 2016, Signal Integrity, Power Integrity, SnP Component

Figure 2. ADS 2016 SnP component reads port names from the file directly onto the symbol, and allows you to choose the pin orientation.


Using S-Parameter Checker isn’t the only way that using S-Parameter files in ADS 2016 is now easier than ever before.


With a new SnP component, port names can be read from the file directly onto the symbol for simulation (Figure 2). This leaves you free to choose the orientation of your pins so that all inputs are on one side and all outputs are on the other side—and that means no more crossing of wires. Once that step is accomplished, all you have to do is view, edit, place, simulate, and plot (Figure 3).

SIPro, PIPro, ADS 2016, S-Parameter Checker, SnP component, S-Parameter, Keysight EEsof EDA

Figure 3. Using S-Parameter Checker and SnP component, using an S-parameter file for a part is now easier than ever before.


For more information on overcoming this and other design challenges, check out 8 Ways ADS 2016 Helps You Overcome Signal and Power Integrity Challenges.

Apply for a free trial

Here’s something that shouldn’t come as a shock to you: data rates are increasing. In fact, multi-gigabit data rates for modern network infrastructure and devices aren’t just an occasional occurrence, they are now the norm. As those data rates increase, you would expect that your electromagnetic (EM) simulation continues to deliver accurate results, but that isn’t always the case. Consequently, picking the right EM technology is now all the more important.


In that regard, you have a few options. Full-wave general purpose EM simulation tools, for example, can be used to achieve the desired accuracy. Faster hybrid simulators, specifically tuned to the requirements of low-GHz applications, can also be used. However, the scale and complexity of today’s PCB designs limits the effectiveness of the 3D-EM simulation; especially when it comes to signal integrity (SI) analysis. If the PCBs are densely routed, it may take hours of engineering time to manually simplify a layout, cookie-cut the signal nets, and optimize the meshing to achieve accurate results. Worse yet, there is always the question of whether or not the simulation correlates well with measurement and if any EM effects were missed?


What’s the solution to these challenges? For those SI engineers looking for an answer, an EM analysis solution specifically targeted at dealing with high-speed links on large, complex high-speed PCBs is a good place to start.

 SIPro, ADS 2016, signal integrity

Figure 1. With ADS’s SIPro, signal analysis can be completed in just a fraction of the time it would take using a more traditional approach.


SI EM analysis, available in ADS 2016 SIPro solution, utilizes composite EM technology to deliver pure-EM analysis. By doing so, it captures all relevant EM effects, such as via-via coupling and via to microstrip transitions. A net-driven interface allows you to select only those nets you want to simulate, along with the relevant power and ground planes, as well as components. With no engineering effort or time needed on your part to manually edit or manipulate layout objects, you can quickly perform EM simulation. You can even automatically set up ports. It’s a workflow that can take you from layout to results in under 20 clicks (Figure 1).

SIPro, ADS 2016, signal integrity         

Figure 2. SIPro delivers results approaching the accuracy of full-wave 3D-EM solutions, but in a fraction of the time.


Once EM simulation is finished, you can plot the S-parameters, TDR/TDT and crosstalk to quickly determine if your EM model is sufficiently characterized and if your channel is performing as expected (Figure 2). Furthermore, with a single-click, automatic schematic generation back-annotates the EM model, making it ready for you to use in both transient and channel simulations.


For more information on overcoming this and other signal integrity or power integrity challenges, check out 8 Ways ADS 2016 Helps You Overcome Signal and Power Integrity Challenges.


This year DDR4 shipments are expected to reach 35% of total dynamic random access memory (DRAM) shipments, an increase of 15% from last year (source: IC Insights). 


The top speeds of these DRAM devices bring forth a legion of signal integrity and power integrity concerns that if the designer doesn't approach systematically, will leave margin, performance and reliability on the table.  At the present, top speeds for DDR4 (without overclocking) are 3200MT/s, and an interesting point to note is that this top rate is expected to double when the next generation technology comes through (the DDR5 spec is currently being worked on in JEDEC). 


Minimizing reflections, crosstalk, and selecting the optimum termination choices are critical now, and will become paramount in the near future.  

DDR4, Keysight ADS, signal integrity, simulation

Reaching confidence in a DDR4 design requires setting up an Electromagnetic (EM) simulation of the PCB layout.


A key step to reaching confidence in a design is setting up an Electromagnetic (EM) simulation of the PCB layout, to catch issues before fabricating the board.  This requires high-frequency accuracy of an EM solver in a productive workflow. This is especially important for DDR, where the number of IOs are exceptionally high.  Setting up ports and sifting through data has been onerous in EM simulation solutions in the past.  


Starting a design in DDR4? 8 steps to ensure success


  1. Begin with a DDR bus simulation in schematic, typically for a single byte lane of data (DQ) lines with data strobe, and a similar setup for the full-rate command/address lines, using your desired substrate stackup.  The starting point is usually a reference design from the CPU/Memory Controller vendor, but of course you are not constrained to this.  The bus simulation will allow you to easily sweep multiple parameters at once (for instance: On Die Termination values for the DRAM IOs), such that you identify the physical layout constraints for the link, or optimize the interconnects for higher performance and/or more margin.  DDR bus simulation allows you to quickly see what the dominant factors are, by enabling/disabling crosstalk aggressors, and looking at the eye diagram at any point in the chain. DDR4, pre-layout, ADS, Keysight ADS, jitter, inter-symbol interference

Pre-layout exploration is important to look for things such as inter-symbol interference in the channel, random and deterministic jitter, and degredation due to VCC bounce.


  1. Swap to a Transient simulation on the same schematic, and check that the time-domain measurements like skew, overshoot, undershoot, and timing have enough margin to the specification.     
  2. Create the PCB layout once an optimized design has been reached. The finished (or partially-finished layout) can be imported to a design tool for an EM simulation (for example, to ADS for simulation with SIPro).DDR4, ADS, EM simulation

A critical step to a successful DDR4 design is performing and EM simulation to catch issues before fabrication.


  1. Perform an EM simulation to capture any of the unforeseen issues that were not present in the schematic.  Issues like voids in the ground plane, or crosstalk in the via pin fields being worse than expected. 
  2. Inspect the resulting S-parameter data for the PCB for quality and any obvious issues that may have been found in the layout. E.g. transmission on one line sees more loss than the others, or has a resonance when the others do not.  With near-end and far-end crosstalk responses plotted, are there any that stand out as being much higher crosstalk levels than the rest?  Note: If the power distribution network design is ready, this can be easily added to the same EM simulation as well.
  3. Replace the physical interconnect models with the new EM model in the schematic from step 1. Run a DDR bus simulation to verify the margin to the Receive BER mask is still acceptable.  A BER of 1e-18 is required for command/address lines, which is why the statistical bus simulation is so important.
  4. Run a transient simulation of the same schematic, whereby the power supplied to the Tx and Rx components (represented as power-aware IBIS models) can be realistic, traveling through the EM model of the PDN before arriving at the IC. In this way, Vcc sag & Ground bounce are modeled, and the eye diagram will be noisier.  Measuring the added jitter and peak-peak amplitude noise, means that this information can be used to adjust the Rx BER mask as used in step 6. 
  5. Analyze the worst-case traces with a DDR4 compliance test bench to cement confident in your design procedure. A compliance test bench uses the same compliance test software on the simulated waveforms as is used on the test bench with your first prototype system, now fabricated and ready to probe.    DDR4, compliance test bench, Oscilloscope, ADS

Before committing the board to prototype, the waveforms can be used with software to perform a DDR4 Compliance Test.


Keysight has multiple design flow examples for DDR4 and hands-on workshops, please visit the link below for more information.    

Download free 30-day trial of ADS!