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15 Posts authored by: Colin Warwick Employee

The Tower of Babel (Genesis 11:1-9) is a story to explain why the world's peoples speak different languages:


The explanation of why the world's circuit simulators speak different languages is more mundane...


There were many attempts at circuit simulation programs before, but one called Simulation Program with Integrated Circuit Emphasis (SPICE) really pushed all the others out soon after it "... was announced to the world … in Waterloo, Canada at the Sixteenth Midwest Symposium on Circuit Theory on April 12, 1973. The paper was presented by none other than Professor Donald O. Pederson of the University of California, Berkeley." (As one of the co-authors Larry Nagel recalls in his retrospective, "Life of SPICE.")


Happy Birthday, SPICE, 46 years old today!


The original SPICE, now called Berkeley SPICE, went through many versions but in all of them the input "deck" (yes, early computer programs were on a deck of punched cards) remained fairly consistent. The circuit you wanted to solve was in the form of a netlist:

*** NETLIST Description ***
M1 vdd ng 0 0 nm W=3u L=3u
R1 in ng 50
Vdd vdd 0 5
Vin in 0 2.5

Some simple models were "atomic" (R for resistor, V for voltage source), other more complex ones (M) refered to a separate .model line:

*** MODEL Descriptions ***
.model nm NMOS level=2 VT0=0.7 KP=80e-6 LAMBDA=0.01

Then you just had to specify what analysis you wanted and where the last card was:

*** SIMULATION Commands ***



But then the Tower of SPICE got too close to the heavens and suffered a set back as punishment for its hubris! Here is what happened: UCB had an open source policy that enabled anyone to freely modify, compile, and sell the resulting binary. Twins siblings Ashawna and Kim Hailey founded Meta Software to sell HSPICE. (It's now owned by Synopsys). A version by Microsim for PC was called PSPICE. (It's now owned by Cadence). Linear Tech (now part of ADI) had LTspice. There was ISPICE, ISSPICE, XSPICE and of course Keysight's (then HP's) very own high frequency HFSPICE (since renamed ADS Transient Convolution).


The benefit was free market competition to improve it, but a frustrating side effect was the input dialect diverged to the point that a netlist written for one version would no longer run on any other.


So, just like human languages post-Babel, translators came in. ADS has a part called (you guessed it) "netlist translator" or nettrans. If you have a PSPICE/LTspice netlist model that consists of open, basic components such as RLC, VCCS, industry-standard models and so on, then we can import it. If it contains encrypted parts or proprietary compiled C-code models we cannot. Sometimes there is a workaround: we can find a similar model, or tweak the syntax to make it work. Ask us!


What about HSPICE and Spectre? For those, translation was found to be inadequate so we added "compatibility modes" to our simulator that actually change its internal behavior so it can consume the foreign netlist directly and without translation. Again, there are a few proprietary features that we can't support, but we'll do our best to help you. Some things really are Lost in Translation!

Want to find out how to design a smaller, lighter, and lower cost switched-mode power supply? Please register for our Keysight Engineering Education (KEE) Webinar on this topic, that we will present on Wednesday January 30th 2019, 10AM Pacific/1PM Eastern.


Bring your questions to our live Q&A session!


Registration link:


Engineers building switched-mode power supplies into their systems are demanding lower cost, smaller size, and lighter weight. In general, faster switching speed – high di/dt in the industry jargon -- enables smaller, lighter, and cheaper versions to be made. Learn how to identify and control the post-layout parasitic effects that degrade switched-mode power supply performance to design a more efficient switched-mode power supply.   

Three Key Learnings: 

  • Understand the limitations to traditional switched-mode power supply design. 
  • Learn to identify spike voltages induced across layout parasitics. 
  • Know how and why to do post-layout analysis before sending the layout to fabrication.

Hope to see you there!

When you create a Verilog-A version of a VHDL analog model, you'll want to verify that the two match. A convenient way to do this is to compare things like I-V curves, for example. The ADS simulator can place data for the I-V curve of your Verilog-A model directly into the dataset used by ADS Data Display. But how do you get the VHDL version in? First you'll have to export the data from your VHDL simulator. The most convenient format for ADS to read is a tab separated plain text file. However, for ADS to make sense of the data, it also needs information in the form of a header and a footer, so you might need to open up the raw data in a plain text editor and type them those in manually. There are several styles and formats possible, but let's pick a simple one but very flexible one. (The technical name is "Generic MDIF" if you want read the full specification in the doc.)


See the sample below. Lines that begin with ! are comments. The beginning of an array of data is marked with BEGIN nameofmydata. The next line, beginning with a %, specifies a column name and its data type e.g. Vd(real). You need one specification per column of data.

Then you have the tab separated data itself, two columns in my case. Finally, you need an END line. Here is a complete example:

!Optional comment like "this data was generated by running a VHDL model"
% Vd(real) Id(real)
-1.000E+00 -1.000E-13
-9.000E-01 -1.000E-13
-8.000E-01 -1.000E-13
-7.000E-01 -1.000E-13
-6.000E-01 -1.000E-13
-5.000E-01 -1.000E-13
-4.000E-01 -1.000E-13
-3.000E-01 -1.000E-13
-2.000E-01 -9.987E-14
-1.000E-01 -9.643E-14
0.000E+00 0.000E+00
1.000E-01 2.703E-12
2.000E-01 7.848E-11
3.000E-01 2.203E-09
4.000E-01 6.174E-08
5.000E-01 1.731E-06
6.000E-01 4.852E-05
7.000E-01 1.360E-03
8.000E-01 3.812E-02
9.000E-01 1.069E+00
1.000E+00 2.996E+01


To import its data via the Data File Tool, it is convenient to place the plain text file in the data folder of your workspace. The file name extension should be *.mdf . For example, if your workspace is C:\Users\cwarwick\Workspaces\shared_wrk, its data folder is C:\Users\cwarwick\Workspaces\shared_wrk\data and so the full path of your data file should be something like C:\Users\cwarwick\Workspaces\shared_wrk\data\myvhdldata.mdf 

  1. From the Data Display menu bar, select Tools-->Data File Tool.
  2. From the Data File Tool dialog box, set the "Mode" radio button to "Read data file into dataset."
  3. Click on the "Browse...' and select your data file.
  4. From the "File format to read" list, select "MDIF"
  5. From the MDIF sub type list, select the last option "Generic MDIF"
  6. In the "Dataset name" text box type a name such as "VHDLcompare"
  7. Click on the "Read File' button.
  8. From the Data Display menu bar, select Insert-->Plot...
  9. Click anywhere on the drawing canvas.
  10. In the "Plot Trace & Attributes" dialog box, select VHDLcompare (or what ever name you gave it) from the drop down list.
  11. For an I-V type plot, first select the name of the current vector (Id in our example), then click on the ">>Add Vs..>>" button, then select the corresponding voltage vector (Vd in our case). Click on OK, to dismiss, and OK again to dismiss the dialog box and see your plot.



You can overlay data from other datasets such datasets generated by simulations including your Verilog-A model and check that the models match.

In Part 1 we only translated a simple resistor. Let's look at a more complicated model, a diode with a junction capacitance that varies with voltage. Here is the model in VHDL-A, keywords in bold:

library IEEE, Disciplines;
use Disciplines.electrical_system.all;
use IEEE.math_real.all;
entity diode_cap is
   generic (

      i0: REAL := 0.0; -- amps

      tau: REAL := 0.0; -- seconds

      c0: REAL := 0.0; -- farads

      vj: REAL := 0.0); -- volts
   port (terminal a, k: electrical);
end entity diode_cap;
architecture simple of diode_cap is
   quantity vdiode across idiode, icap through a to k;
   quantity qcap: charge;

      constant vt: REAL := 0.0258; -- thermal voltage at Tj = 300K in volts
   idiode == i0 * (exp(vdiode / vt) - 1.0);
   qcap == tau * idiode - 2.0 * c0 * sqrt(vj**2 - vj * vdiode);
   icap == qcap’dot;
end architecture simple;


It is similar in structure to the resistor example in part 1, but there are three new ideas added:


First, the implicit parallel connection of the two current branches idiode and icap that you can see in the line:

   quantity vdiode across idiode, icap through a to k;

Second, the usage of the "tick dot" notation to apply the time derivative method onto qcap in the line:

   icap == qcap’dot;

Third, charge is a data type in VHDL-A's electrical nature.


My translation to Verilog-A is:

`include "disciplines.vams"

module diode_cap(a, k);
   parameter real i0=0.0; // amps
   parameter real tau=0.0; // seconds
   parameter real c0=0.0; // farads
   parameter real vj=0.0; // volts
   real qcap;
   inout a, k;
   electrical a, k;
   branch (a, k) diode, cap;
   analog begin
      I(diode) <+ i0 * (limexp(V(a,k) / $vt(300)) - 1.0);
      qcap = tau * I(diode) - 2.0 * c0 * sqrt(vj**2 - vj * V(a,k));
      I(cap) <+ ddt(qcap);

Notable differences compared to part 1 and to the VHDL version are:


First, that branch is an explicit keyword in Verilog-A. Here we declare two named branches diode and cap both of which are between nets a and k, which renders them in a parallel (aka shunt) configuration. You can apply the access functions V() and I() to named branches so V(a,k) is the same as V(cap) and V(diode) in our case. (By the way, to connect branches in series instead of parallel, you would declare an internal node, say electrical i; , and write something like branch (a, i) rs, (i, k) diode; )


Second, that the time derivative is a function ddt() not a method. If the capacitance had been a constant c, you could have used I(cap) <+ c * ddt(V(cap));


Third, I used a real to represent charge. There is a Charge nature in the standard include file disciplines.vams Verilog-A but it's not useful in this context. The variable qcap is internal to the model, so we omit the parameter keyword, because we don't want to expose it in the model's parameter list. Because qcap is an ordinary variable, we cannot use the <+ contribution operator: we must use the assignment operator = .  For this reason, the order of the statements is important. The qcap assignment must be placed before the contribution statement that uses the result. This is a subtle but important difference between Verilog and VHDL and it is worth your time to ponder it. For a discussion, see page 58 of "The Designer's Guide to Verilog-AMS" by Kundert and Zinke.


Note that I chose to highlight one of the built-in system functions $vt() for the thermal voltage rather than defining a constant.  You can use an explicit temperature like $vt(300) or the simulator temperature by writing $vt($temperature). If you omit the parentheses and argument, simply $vt, it is equivalent to $vt($temperature). By the way, the temperature is in kelvin, so be sure not to accidentally set it to zero! Zero kelvin is non-physical obviously, and besides that it can trigger horrible math library exceptions like divide by zero or zero to the power zero.


Note also that I chose to use limexp() instead of exp(). limexp is short for exponential with limiting. It limits how fast the return value can change from call to call. It often improves simulator convergence versus its cousin, the more usual exp().


In Part 5, I turn to a slightly different topic, namely verification.

In my previous post, I showed you the "all-in-one" method for adding your Verilog-A models to ADS. In this post, I'll show you another method called "shared library." It's a bit more work to set up, but it saves time in the long run because it avoids duplication of effort in each new project. If you give a project workspace to a colleague you have to remember to give the referenced library also. In fact, this shared library method is just good not only for Verilog-A components but also for component models of other types (e.g. netlist-based models/model cards). It's a good method anytime you have component models that are common to several projects. Like last time, there are quite a few steps, but each one is really easy.

Shared Library

  1. Follow steps 1 through 20 of Part 2, except this time, in step 2, name the workspace something like shared_wrk. Alternatively, make a copy of all_in1_wrk, rename it shared_wrk, and then delete the testbench cell.
  2. In the Main window, select the Library View tab. When you created the workspace, ADS automatically created a default library under it. The default name is created by replacing the _wrk suffix with a _lib suffix. So in our case it is called shared_lib. Right click on the library and select Configure Library... from the popup context menu.
  3. In the Library Configuration Editor, Simulation tab, click on the Browse... button to the right of the Verilog-A directory edit box. Browse up one level and select the veriloga folder. Alternatively, you can just type ..\veriloga into the edit box. The relative path-name is preferred over an absolute path because if you give the library to a colleague, they might install it with different root name. Dismiss the Library Configuration Editor by clicking on the OK button. It reminds you that changes will take effect next time you open it. Click OK.
  4. From the main window menu bar, select File-->Close Workspace. We are done with the shared library for now. Let's imagine we are starting the first of several projects that will refer to the shared library. 
  5. From the ADS Main Window menu bar, select File-->New-->Workspace...
  6. From the New Workspace dialog box, give it a name like project1_wrk and then click the Create Workspace button.
  7. From the Main window menu bar, select File-->Manage Libraries...
  8. From the Manage Libraries dialog box, click on the "Add Library Definition File..." button.
  9. From the Select Library Definition File browser, navigate to the previous workspace (i.e. your shared_wrk folder) and locate and select a file called lib.defs then click the Open button.
  10. Dismiss the Manage Libraries dialog box by clicking on the Close button.
  11. In the Main window Folder View tab, click on the little arrow by the resistor cell folder. You should see the symbol view of the cell.
  12. From the Main window menu bar, select File-->New-->Schematic... and name its cell something like testbench.
  13. Create Arrange the Main window and the new testbench schematic window side-by-side.
  14. Click and drag the resistor symbol from the Main window to the testbench schematic window. Instantiate your resistor by clicking anywhere on the schematic canvas. Set it to 2 ohms.
  15. Create a simple testbench like this:
  16. Click on the Simulate icon or select Simulate-->Simulate or just hit the F7 shortcut key. The first time you simulate, there is a short pause while ADS compiles the Verilog code. It saves the compiled model, so if you don't touch the code, there is no need to re-compile the next time you run it.
  17. From the Data Display window, insert a plot, and select the Vout and branch current (_ub_p_n_i) traces:
    voltage and current through 2 ohm resistor
    I added some markers and played around with the axis and trace settings.

Success! Now you create project_2, project_3 and so on. Repeat steps 5-17 for each new project to refer to your shared library thus reusing it.


In the next posting, we'll return to the main topic: how to translate the analog parts of VHDL-AMS to Verilog-A. Part 1 was a resistor. Part 4 is a comparison of how the two languages handle time derivatives and internal branches.

In my previous post, showed you how to create the Verilog-A code for a component model. In this post I'll show you how to import the code into ADS. If you don't have access to ADS or you're not familiar with it, I suggest you read our Quick Start Guide first.


There are two strategies for adding a model to an ADS workspace, let's call them "all-in-one" and "shared library" methods. "All-in-one" is the simplest and as the same suggests it is self-contained. "Shared library" is a bit more work to set up, but it saves time in the long run because you can reference the same library from each new project, and avoid having to recreate it every time.

I cover the all-in-one method in this post and the shared library in the next.

(Side note: There is also a further Verilog-A flow in the W2319 ADS RFIC Interoperability Element, but I won't be covering it in this series. If you are interested, the doc page is here.) 

All-in-one method

  1. Launch ADS. From the ADS Main Window menu bar, select File-->New-->Workspace
  2. In the "New Workspace" dialog box, give your new workspace a name such as all_in1_wrk 
  3. Click on the "Create Workspace" button.
  4. In the Main window "Folder view" tab, you will see a workspace folder whose name ends in ...\all_in1_wrk. Right click on it and select the last option in the pop up context menu, namely "Explore In File System".
  5. Assuming Windows OS, File Explorer opens in the workspace's folder on your file system. Right click on a blank space in the right panel and select New-->Folder. It is best to name the folder veriloga because then it will be on the default search path that the Verilog-A compiler looks in.
  6. Open your new folder and, using copy-paste and your favorite plain text editor, create the file containing the Verilog-A source code from Part 1. Name the file (The first part can be anything convenient, but the file extension must be either *.va or *.vams for the compiler to recognize it.) You can close your text editor and Windows Explorer if you like.  
  7. Go back to the ADS Main window and from its menu bar, select File-->New-->Symbol view...
  8. In the "New Symbol" dialog box, overwrite the default cell name (cell_1) with  resistor. Note that you are creating not only a view but also a cell. A cell is a container that holds one or more views of a component or a circuit. You never view or edit the cell directly but instead you view and edit it via one of its views. It is important that the cell name, resistor, matches the module name, resistor, in the Verilog code.
  9. In this "New Symbol" dialog box, click the "Create Symbol" button. Two new windows open: The Symbol Generator dialog box and the Symbol canvas itself.
  10. In the "Symbol Generator" dialog box, make sure you are on the Copy/Modify tab, then select "Lumped-Components" from the "Symbol category" drop down list. (Side note: if you want to use the Auto-Generate tab instead, you'll have to add an extra step to specify the number of pins. See Note 1 at the bottom of the this post.) Click on the resistor icon. The "Symbol name" edit box will populate as ads_rflib:R . Click OK to dismiss the "Symbol Generator" dialog box. By the way, you can draw your own symbol if there is no suitable one already: Search for the "Draw a Custom Symbol" topic in the doc.
  11. In the Symbol drawing canvas you can see the symbol as been automatically created, with pins 1 and 2 with default names P1 and P2. Double click on each pin in turn and change the name to match those listed in the Verilog code module resistor(p, n); i.e. set the name of pin 1 and 2, to p and n, respectively.
  12. From the Symbol window menu bar select File-->Design Parameters.
  13. In the "Design Parameters" dialog box's "General Cell Definition" tab, set the "Component Instance Name" to whatever prefix you want instances to have, R for example. Instances will be given default names R1, R2, R3, etc.
  14. Important! Uncheck the "Subcircuit" check box. (If you are curious, the difference between a subcircuit and a leaf node is that you can push into the hierarchy of an instance of a subcircuit, but not into a leaf node. Try it! Right click on any instance of a component in a schematic and select "Push Into Hierarchy" from its pop up context menu. If the instance is a subcircuit, the subcircuit will open. If not, you get a "Cannot push into this instance" error. This check box tells the netlister which type (subcircuit or leaf node) it is dealing with, so it can traverse the hierarchy correctly.)
  15. In the Simulation frame, select "Subnetwork" from the Model drop down list. (Wait a minute Colin, I thought you told me in the last step that what we are building is not a subcircuit? Well, it is isn't. It isn't a subcircuit, but it is a subnetwork. Yikes! A subnetwork is in contrast to a built-in component. The third option "Model" is for non-simulatable items like text annotations.) 
  16. Select the "Cell Parameters" tab of the "Design Parameters" dialog box. Remember the line parameter real r=0.0; in the Verilog code? Here is where you connect to it. In the Edit Parameter: Parameter Name edit box type r, leave the Value Type as "Real", set Parameter Type/Unit to Resistance, and type something helpful like "Resistance in ohms" for the parameter description. It is best to leave the Default Value blank. You can put a value in there, but it will override the default value in the Verilog-A file, which might be confusing if the two values get out of sync at some point. 
  17. Look to the left side of the same tab, and click on the "Add" button. The r parameter will be added to the parameter list box.
  18. Click OK to dismiss the "Design Parameters" dialog box.
  19. Go back to the "Symbol" window menu bar, and select File-->Save. We are done with this window, so you can close it if you like.
  20. Go back to the ADS Main Window, Folder View tab. Click on the little arrow to open your resistor cell folder. You can see that your cell now has one view: symbol.
  21. The next few steps prepares a testbench to instantiate it on. From the ADS Main Window menu bar, create a schematic view of a new cell by selecting "File-->New--Schematic...". This will be our top-level cell. Call this new cell "testbench."
  22. Arrange the Main window and the new testbench schematic window side-by-side.
  23. Click, hold, and drag your resistor symbol from the Main window's Folder view tab across your screen to the testbench schematic window. Instantiate your resistor by clicking anywhere on the testbench schematic canvas. Hit the ESC key to leave instantiation mode. Set the resistance to 2.0 ohms.
  24. Create a simple testbench like this:
  25. Click on the Simulate icon or select Simulate-->Simulate or just hit the F7 shortcut key. The first time you simulate, there is a short pause while ADS compiles the Verilog code. It saves the compiled model, so if you don't touch the code, there is no need to re-compile the next time you run it.
  26. From the Data Display window, insert a plot, and select the Vout and branch current (_ub_p_n_i) traces:
    voltage and current through 2 ohm resistor


The next posting, shows you the shared library method. A lot of the steps are the same, except we create separate workspaces for our component library and our test bench, and link the two.


Note 1: In Step 10 above, if you want to use the Auto-Generate tab instead of the Copy/Modify tab, you'll have to add an extra step to specify the number of pins. Create a schematic view in the cell you are working on, then place one pin for every port in the Verilog-A function argument list e.g. 2 pins for module resistor(p, n); . It looks odd to have a schematic with nothin but unconnected pins, but trust me it works! Then save the schematic and go back the symbol view Auto-Generate tab.

Verilog-AMS and VHDL-AMS are hardware description languages, capable of describing mixed-signal (i.e. analog and digital) hardware. In this series of postings, we’ll be talking about Verilog-A (i.e. the officially defined subset of Verilog-AMS that supports analog) and “VHDL-A” (not officially defined, but defined here as "the parts of VHDL-AMS that supports analog").


ADS support Verilog-A but not VHDL-A so this series of posting will explain how to create a Verilog-A model if all you have to start from is a VHDL-A model. It isn’t a comprehensive Verilog or VHDL reference manual: you can find plenty of those by searching on the Internet. The idea here is to get you started. You’ll have to refer to those other resources for the in-depth information. Another good resource is Best Practices for Compact Modeling in Verilog-A, J. Electron Devices Soc. (Aug. 2015) by Colin C. McAndrew et al. It's not about how to code models in Verilog-A, it's about how to code them well. 


Let jump right in and compare how the two languages express the simplest possible analog component, the resistor:


Code fragment 1a: Resistor in VHDL-A

use electrical_system.all;
entity resistor is
   generic (r: real := 0.0);
   port(terminal p, n: electrical);
end entity resistor;
architecture signal_flow of resistor is
   quantity vr across ir through p to n;
   vr == ir * r;
end architecture signal_flow;


Code fragment 1b: Resistor in Verilog-A

`include "disciplines.vams"

module resistor(p, n);
     parameter real r=0.0;
     inout p, n;
     electrical p, n;
     analog begin
           V(p,n) <+ I(p,n)  * r;

Keywords are in bold. The other identifiers are defined in the code itself, or in the included libraries. For example in both langauges, the identifier electrical is not a keyword: it is defined in a standard library. VHDL-A has:

use electrical_system.all;

…and Verilog-A has:

`include "disciplines.vams"

We won’t go into the contents of these yet. Suffice it to say that they serve a similar purpose, namely to save you from writing the basic “plumbing” required to set up your model.


The two languages diverge in the next lines.


VHDL-A divides the code up into entity and architecture sections. The entity keyword is used to introduce the description of the interface of the component. Here we define ports p and n and a parameter, r. Then, the architecture keyword is used to introduce the description of its internal details. An entity can have more than one architecture ("polymorphism"), so we have to give each one a name, signal_flow in this case, so we can specify which morphology we want to use later on. To implement an architecture with ohmic behavior, we first state explicitly that the voltage V and current I are the across and through variables, respectively, of our ports with:

quantity vr across ir through p to n


(Side note: The terminology “through and across variables” comes from the mathematics of the class of problem that all SPICE-like solvers solve, namely differential algebraic equations or DAEs. In Verilog-A, through and across variables like voltage and currents are called "natures" and a pair of related through and across variables is called a "discipline." Voltage and current natures, plus some other information like tolerances, form the electrical discipline. Confusingly, VHDL-A uses the term "nature" for the pair of natures, whereas Verilog-A uses "discipline.")


Then we specify Ohm’s law, V=IR, for the branch constitutive equation:


 vr == ir * r

The "double equal signs" operator implies the simulator should force the equation to be true for every time step in the simulation: it isn’t a one-time assignment like the a = b in C and Java nor the a := b in Pascal and ADA. (And it isn't at all like the equality test A == B in C and Java.)


In contrast, Verilog-A combines the entity/architecture ideas. The module keyword is used to introduce both interface (the parameter, inout, and electrical lines) and the internals (the block that is bounded by analog begin end ).

The line:

V(p,n) <+ I(p,n) * r; called a contribution statement. It is similar to the one in VHDL with double equals == except that the operator in Verilog-A is <+ . Why <+ ? It's because Verilog-A allows multiple contributions to add to the voltage V(p,n). For example,

V(p,n) <+ V(p2,n2);

V(p,n) <+ V(p3,n3);

…is equivalent to:

V(p,n) <+ V(p2,n2)+ V(p3,n3);


Similar to == in VHDL, <+ in Verilog-A implies the simulator should do whatever it takes (iteration!) to force the equation to be true for every time step in the simulation.


In Verilog-A, there is no need for a line like quantity vr across ir through p to n that we had in VHDL because the so-called access functions, V() and I(), are defined in the `included disciplines.vams header file and thereby associated with any instances of the electrical discipline.


So, that's a component. Part 2 shows you how include the Verilog-A version into ADS create a testbench that instantiates the component, adds some stimulus, and shows you the response.

Please register for a webinar I'm presenting Sept 6th, 2018 at 1PM EDT. The title is Designing Switched-Mode Power Supplies in the High di/dt Era. I hope you will attend!

This Case Study highlights work published in a recent paper in IEEE Power Electronics Magazine entitled Utilizing Modern Design Methodologies for Wide-Bandgap Power Electronics by my colleague here at Keysight EEsof EDA, Chris Mueth, and by Rakesh K. Lal of Transphorm, Inc. The high di/dt and dV/dt edges in switched-mode power supplies (SMPSs) combined with layout parasitics can create unwanted voltage spikes. The authors demonstrate that EM-circuit co-simulation can predict these effects. With the insights from this predictive tool in hand, they rapidly explore the design space and mitigate the impairment. The time and money spent on board spins is reduced and the time to market improved.

The Challenge

Since GaN switches are intrinsically very fast, one can have a very high change in voltage versus a given change in time (dv/dt) (>300 V/ns) and a change in current versus a given change in time (di/dt) (>5 A/ns). So, designers need to use good design practice for high-frequency layouts. Three cardinal rules that apply are:

  • Minimize capacitances to ground or other nodes at high dv/dt nodes to minimize Ispike = C dV/dt
  • Minimize parasitic inductance in high di/dt branches to minimize Vspike = L di/dt
  • Guard or shield high-impedance signal nodes, such as the gate of a drive transistor with appropriate guard rings and shields.

Physical prototypes are costly and time consuming to build and don't give insight into details like current crowding (which is indicative of excess inductance). But virtual prototyping in a tool like ADS (which allows EM circuit co-simulation) do exactly this. 


The Solution

The authors used ADS to gain insight into design weaknesses. The key point here is that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along with the effects of the layout. You can plot the voltage spikes and do "what if..." design space exploration, such as using a ground plane for the return current, to minimize their effects.


The Results


The Transphorm reference design analysis used the Momentum method of moments EM field solver. The EM-model extraction took roughly one hour. The tool automatically creates the components representing the layout from the port-to-port network parameters generated by the EM field solver. The analysis tool then simulated the circuit schematic including the extracted model in the time domain.


After experimenting with various "virtual prototypes", the final reference design utilized two power planes, which were poured onto two different PCB layers. This provided the best possible reduction in power plane inductive parasitics. In addition, the power planes were placed close together and provided an additional capacitance benefit. As a best practice, the ground layer was located under the main trace routing layer to provide additional capacitance to help reduce the stray inductance of these traces. 


The reference design produced an efficiency of 98.5% for the buck half-bridge configuration. This correlates well with the 98.3% efficiency seen in the simulation. The gate-driver waveforms also correlated well.


Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!


Best regards,

-- Colin


PS Here's the link to request an ADS evaluation license if you want to try it.

The trend in switched-mode power supplies is to use wide band gap devices because these enable a higher switching frequency and higher edge speeds (the “di/dt” of the switched loop). These two in turn enable a smaller, lighter, cheaper power supply because the energy storage capacitors and magnetics can be smaller if you top them off more frequently. The higher edge speeds enable higher efficiency because there’s less heat dissipated when you have lower switching losses because the transistors spend less time in the dissipative cross over region.


These high slew rates come with a dark side, in particular the large spike voltage and noise generated by the layout parasitics, particularly inductance, of the PCB layout traces. This phenomenon is often called conductive electromagnetic interference (conducted EMI).


My colleague, Andy Howard, talked about how to deal with this a while back in his video entitled “How to Design DC-to-DC Power Converters”, but a frequently asked question was “When should I start to worry about layout parasitics inductance? Is there a quick rule of thumb that says kind of ‘Caution: Further investigation’s needed?’” The answer is "Yes!" and this follow up video is about how to make these estimates. Here's the link:


How to Estimate Voltage Spikes from Layout Parasitic Inductance in Switched-Mode Power Supplies


Layout parasitics cause spike voltages in the switched loop of a switched-mode power supply

Calling all power electronics engineers! Can you please help me by completing this short survey?

Note: A more polished version of this Case Study is available in PDF format as STMicroelectronics & ESEO Use ADS To Design a 2.45 GHz Wireless Power Scavenging Circuit. There is also slightly different version: Extending the Operating Life of IoT Devices with a Wireless Energy-Harvesting Circuit.


Previously I posted a Case Study about a wireless power scavenging circuit whose impedance matching circuit was built around a high Q quartz crystal resonator. This particular component works best at 24 MHz. One of the comments I received on the LinkedIn syndication of that posting asked about similar circuits, but in the microwave regime. This band is important because there is more ambient RF energy floating around at 1.8 GHz (e.g. GSM1800 from cell towers) and 2.45 GHz (from WiFi) than at 24 MHz. So I searched around and the result is this new Case Study about series of papers by Dhaou Bouchouicha and Mohamed Latrach et al. They are at ST Microelectronics and Ecole Supérieure d'Electronique de l'Ouest (ESEO) in France. The papers include An Experimental Evaluation of Surrounding RF Energy Harvesting Devices and Hybrid Rectenna and Monolithic Integrated Zero-Bias Microwave Rectifier.

The Challenge

To rectify the ambient RF/microwave energy, the matching circuit must put a voltage across the rectifying diode that exceeds the forward voltage drop, typically 0.3V for Schottky diode. The antenna gathers less than a microwatt of power, so we need a big impedance transformation from the antenna impedance (something on the order of the impedance of free space, 377 ohms) to several kiloohms.

The Solution

The authors used ADS co-simulation of the Momentum EM field solver and Harmonic Balance circuit solver to optimize the rectenna (rectifier + antenna) design. They included diode package parasitic models, which enable them to get good correlation between simulation and measurement. By carefully tuning the distance "d" between the matching capacitor and the SMA connector (shown in their figure 3 reproduced below) they optimized the convection efficiency. 


The Results

With a patch antenna with dimensions of about 20 mm on a side, they obtained a DC power of 1.3 microwatts with an input power of 10 microwatts, yielding an efficiency of 13%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

(Note: A more polished version of this posted has now been published as a PDF entitled NCK University Uses ADS to Create an Impedance Matching Method for Wireless Battery Charging)


In a previous Case Study I pointed out work that used a high Q quartz crystal resonator for wireless power transfer at 24 MHz. The load in that case was a switched-mode power converter. But what if you want to charge a battery directly? It's tricky because the resistance, reactance, and the cell voltage of a rechargeable battery all vary dramatically with its state-of-charge. What load do you optimize the matching network for when the load is dynamic? In their paper Direct current driving impedance matching method for rectenna using medical implant communication service band for wireless battery charging, H-W Cheng, Tsung-Chi Yu, and Ching-Hsing Luo of National Cheng Kung University address this problem with a simple yet effective method using Advanced Design System. They also used ADS EM-circuit co-simulation to design the printed circuit antenna.

The Challenge

Within a tiny 14 mm (0.55 inch) diameter disk, the wireless battery charger has to include a printed circuit antenna, matching network, two rectifier diodes, and an LC low pass filter. The received RF power was a mere 10 mW at 405 MHz. The challenge is to recharge the Li-ion cell, which had a 10mA.hour capacity, in 5 hours (a so-called "0.2 C rate"). The charging current was 2 mA but the cell voltage varies from 3.0V (empty) to 4.2V (full) and impedance varies wildly with state-of-charge.

The Solution

The authors employed ADS harmonic balance to simulate the circuit and explore the design space. Using a sweeping method detailed in the referenced paper, they came up with a optimized circuit consisting of only three capacitors, one inductor, two diodes, and of course the PCB itself, which includes not only interconnect but also the antenna, designed using ADS EM-circuit co-simulation.

The Results

Figure 7 of their paper shows the finished implementation. They achieved 76% conversion efficiency of incident power to battery charging power averaged over a five hour charge cycle. Comparable prior work achieve only 50%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

Note: A more polished version of this Case Study is available in PDF format as STMicroelectronics and University of Lyon Predict EMI Using ADS.


This Case Study highlights work in a paper N-Conductor Passive Circuit Modeling for Power Converter Current Prediction and EMI Aspect by Roberto Mrad, Florent Morel, Cael Pillonnet, Christian Vollaire, Phillppe Lombard, and Angelo Nagari. The high di/dt edges in switched-mode power supplies (SMPSs) can create EMI problems especially if the layout has long power and ground traces. To explore the design space, you need a good model of the impairment you are trying to mitigate. Prior modeling work used lumped elements, but these are not great a modeling traces, which are transmission lines. You'd need an infinite number of infinitesimal LC ladder segments to model a trace exactly. Mrad took a leaf out of the RF/microwave playbook and used network parameters instead.

The Challenge

Conducted electromagnetic emissions from switched-mode power supplies (SMPSs) interferes with the adjacent circuits they are powering. To avoid failure, EMI filtering is added. To design cost effective EMI filtering, it is necessary to explore the design space efficiently. Cut-and-try is too time consuming and so simulation is preferred. But to do simulation, you need accurate models and conventional lumped element models of the traces are not adequate.

The Solution

Traces and vias are essentially delay lines (exp(s) in Laplace space) whereas lumped element L's and C's are integrators/differentiators (s or 1/s in Laplace space). For this reason, lumped element ladders are not efficient at modeling traces. Fortunately network parameter models are readily available and work efficiently in both frequency and time domain simulation. They work directly in AC or harmonic balance (HB) frequency domain circuit analysis or via convolution in the time domain. (Convolution is a way of building a time domain delay line model from frequency domain data using a "smart" inverse fast Fourier transform (IFFT).) The authors used Advanced Design System because it handles network parameters both from measurement instruments and from transmission line models.

The Results


The authors obtain excellent correlation with measurement as you can see in Figure 18 of their paper:


They went on to use the model to design a compact and low cost EMI filter using a sophisticated optimization algorithm, also using ADS. That paper is called Discrete Optimization of EMI Filter Using a Genetic Algorithm but we'll save that Case Study for another day.



Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

Being new to power electronics, I've been going back through the literature to find out how engineers use Advanced Design System for their switched-mode power supplies (SMPSs) and wireless power transfer (WPT) systems. I'm going highlight a selection of these in this series of postings I call Case Studies. The first is a paper from 2009 on WPT. I initially posted this on my LinkedIn blog but with the launch of this new blog, I'm migrating over to this new site. A more polished version is available as a PDF "Ericsson and Freiburg U. Design High Q Power Harvesting Circuit Using ADS."

This Case Study is about a paper titled RF Energy Harvesting Design Using High Q Resonators by Xavier Le Polozec of Ericsson and Tolgay Ungan, William Walker, and Leonhard Reindl of the University of Freiburg. Their goal was wireless power of a couple of hundred nanowatts at 1V to power a sensor node. The transmitted power was at 24 MHz. They used ADS harmonic balance to explore the design space particularly around the innovative impedance transformation using a high Q quartz crystal resonator to transform the low voltage from the low impedance antenna to a voltage high enough to overcome the Schottky diode junction voltage (about 0.3V).


The Challenge

The tricky part here is that government regulations generally limit the transmitted power such that the harvesting antenna only receives at most -30 dBm (1 μW). Prior solutions had only ~10% total efficiency. To power their sensor they needed a conversion efficiency > 20%. They added a high Q quartz crystal resonator to introduce an impedance transformation between the antenna and the rectifier. The antenna impedance was 50 ohms so voltage with 1 μW is only about 7 mV, not enough to forward bias the Schottky microwave detector diodes (Avago HSMS-2862). The transformer boosts the voltage so that diodes, used as rectifiers in a half bridge configuration, are forward biased and conducting on their respective positive half cycles. The challenge was to satisfy the impedance matching requirement when the antenna, resonator, and matching components were loaded with the nonlinear diodes.


The Solution

The authors used the ADS Harmonic Balance simulator to help design the impedance matching circuit. Unlike SPICE simulators, which typically only handle linear circuits in the frequency domain ("AC analysis"), ADS Harmonic Balance handles nonlinear effects and gives you the periodic steady state solution without having to wait for the startup transient to die down. In contrast ordinary time domain ("transient analysis") requires this time consuming step. They could quickly explore the design space with a set of trustworthy simulations before committing to fabrication. Once the design was optimized, they invested in building the prototype.


ADS harmonic balance gives us trustworthy simulations before committing to fabrication. We can estimate the influence of each parameter over the global circuit response, tuning and optimizing the circuit before committing to fabrication. We get good correlation with subsequent measurements on hardware.

-- Xavier Le Polozec, Senior Technical Subject Matter Expert, Ericsson


The Results

They achieved excellent correlation with measurement and the circuit delivered the required efficiency. The simulation correctly predicted that the peaks of the family of curves of efficiency versus frequency would shift. The nonlinearity of the diodes cause the peak to shift about 200 Hz as the input power is increased from -50 dBm to -20 dBm. This subtle effect was seen in both simulation and measurement.


An input of only 7 mV rms at 24 MHz (1 μW into the 50 ohm antenna) yielded an output of 1 V DC and a measured overall efficiency of 22.6%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.