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2 Posts authored by: MichelAzarian Employee

Introduced in a separate post, GoldenGate 2017 enhances circuit reliability in RFIC design by checking against electrical (such as voltage and current) and geometrical rules that exist in the PDK and/or rules set by the user. This feature is referred to as safe operating area, or SOA. When GoldenGate 2017 finds out that one of these rules is not met, it will issue a warning in the log file. The RF designer can also track down the failing device(s) in the schematic with the tool’s highlighting feature for an efficient debugging experience.

In analog and RF circuits it is common, for instance, to have different voltage and FET domains, making it easy to have a higher voltage being allowed at some nodes but that same voltage being destructive at other nodes. Traditionally, the check for overvoltage is done manually, which, of course, is not generally reliable and is tedious. The simulation tool can perform this task much more efficiently.

Here is an example where the drain of the transistor sees a slight overvoltage that is not high enough to damage the transistor right away, making the oversight hard to uncover during chip evaluation. However, ignoring this slight overvoltage will cause reliability issues down the road, the type that gives semiconductor manufacturers nightmares. GoldenGate 2017 eliminates these fears. It checks against PDK rules by reading the asserts in the kit and it also allows the user to set his or her own rules to check against, enhancing overall reliability.

GoldenGate 2017 integrates the SOA functionality in a well-designed fashion, making it efficient for RFIC designers to check against rules. Besides printing assert violations in the simulation log file, GoldenGate’s “Violation Display” GUI makes the management of rule violation a breeze by displaying a summary of rule checks. Further debugging is straightforward and is done by expanding the details in the same window. Highlighting the violating device(s) in the schematic is also possible at this stage with the click of a mouse button.

Furthermore, results from sweep runs can be expanded into a separate display window for convenient study and comparison. The tables dynamically update column entries to include only relevant data and to keep the table size manageable.

Do you work on RFIC design and have not tried GoldenGate yet? Download your free trial and discover how this world-class circuit simulation tool can help optimize your design process and resolve your circuit simulation challenges.

GoldenGate, offered by Keysight EEsof EDA, is the best-in-class RFIC simulation tool inside the Cadence Virtuoso design environment. For many years, RF designers have relied on GoldenGate to solve their challenging problems, and have benefited from its robust simulation convergence and fast simulation capabilities to fully characterize their transceiver designs prior to tape-out.

GoldenGate offers powerful RFIC simulation solutions. Here are some of its characteristics:

  • Best-in-Class RF Circuit Simulation
    • Provides the most advanced steady-state (including harmonic balance, time balance, time shooting, and hybrid) and envelope (hybrid time-/frequency-domain nonlinear) solvers for design and verification of RFICs within the Cadence Virtuoso environment
    • Supports all large- and small-signal RF and transient analyses including large-signal stability and full X-parameter modeling and simulation
  • Advanced Analysis Support
    • Offers a wide variety of capabilities, such as Monte Carlo, Corners, and Fast Mismatch & Yield Contributor, to fully explore, analyze, and optimize designs before tape-out, minimizing the time and expense of re-spins
    • Includes a unique transistor-level PLL jitter and noise analysis option
  • Automation and Usability
    • Accelerates design and verification by providing a number of built-in and easily accessible multi-dimensional sweep, optimization, Monte Carlo, and load-pull tools along with simulation management capabilities
    • Automates EVM, ACPR, gain compression, IP3, and load-pull analyses
  • RF to mm-Wave Design Support
    • Provides access to ADS Data Display with dedicated RF templates and adsLib with over 150 RF distributed-element library components
    • Handles large S-parameter blocks with Multi-Threaded Convolution
  • Wireless Standard-Compliant Design
    • Enables scalable system-level solutions from RF architecture exploration through end-to-end verification with links to SystemVue and Ptolemy
    • Verifies full radio functionality using Keysight's comprehensive library of standard-based wireless verification intellectual property (IP) to accelerate the validation of complex RFICs; wireless libraries for 5G, Bluetooth, LTE, WCDMA, WiMAX, DTV, etc.

 

Keysight EDA has just released GoldenGate 2017, which introduces the following new features:

  • Safe Operating Area (SOA) – With SOA, GoldenGate 2017 enhances circuit reliability by automatically ensuring all devices operate within their safe operating areas – electrical or geometrical rules set by the PDK and/or the user. GoldenGate 2017 produces appropriate warnings, and highlights the failing devices in the schematic, simplifying the debugging process. This feature replaces tedious and unreliable manual checks. SOA is covered in more detail in a separate post.
  • TSMC Model Interface (TMI) – The use of the new and fast TSMC silicon processes – 16nm FinFET or later – which all require TMI support, makes it possible to design mm-wave circuits with silicon. Doing so enables the mass production of transceivers employed by systems adhering to the upcoming communications standards. Now that GoldenGate supports TMI, users can take full advantage of many of GoldenGate’s strengths, such as robust simulation convergence and fast simulation speed, while designing the latest and greatest circuits. It is worth mentioning that GoldenGate’s implementation of TMI also supports the circuit aging feature of TMI.
  • Simulation Speed Improvement – GoldenGate 2017 significantly improves its envelope transient simulation time and further establishes itself in the efficient simulation realm by introducing 4x parallel threading. Relatively long envelope transient simulation runs benefit the most, and that is where speed matters the most. The following table showcases a few sample envelope transient test runs.

 

Test Case

Wall Time prior to GoldenGate 2017

GoldenGate 2017 Wall Time

Wall Time Improvement

White Noise, ET

3.57hrs

1.01hrs

3.5x

Power Amplifier ACPR, ET 3

5.08hrs

1.86hrs

2.7x

Unit NPort Recurs Var Step, ET

2.39hrs

0.86hrs

2.8x

Level 3 ET

1.24hrs

0.42hrs

3.0x

 

  • New and Updated Model Support – GoldenGate 2017 adds support for the following models: BSIM-IMG 102.6.1, 102.7, and 102.8, BSIM-CMG 106.1, 107, 108, and 110, BSIM-CMG Level = 72, BSIMSOI 4.4, CMC Diode, MOSVAR 1.3, Leti-UTSOI 2.20, HiSIM HV 2.10 and 2.3.1, HiSIM 2.9.0, HICUM L0 1.32, and HICUM L2 2.34

 

   GoldenGate is part of Keysight's RFIC solution that also includes Momentum for 3-D planar electromagnetic simulation and Advanced Design System (ADS) for linking the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow. GoldenGate 2017 is fully compatible with the following Cadence versions:

  • IC 5.1.0 and all subversions
  • IC 6.1.5, 6.1.6, 6.1.7, and all subversions
  • ICADV 12.1 and 12.2

 

   Do you work on RFIC design and have not tried GoldenGate yet? Download your free trial and discover how this world-class circuit simulation tool can help optimize your design process and resolve your circuit simulation challenges.