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32 Posts authored by: KeysightEEsofEDA Employee

In the past, the pre-manufacture design could be simulated and tested using compliance tools from an EDA vendor. And the post-manufacture prototype could be bench tested using compliance tools from test and measurement instrument vendors. However, because of subtle differences between the two vendor’s independent approaches to compliance, it was almost impossible to correlate the two.


This opened the possibility of the pre-manufacture design passing and the post-manufacture prototype failing, necessitating a time-consuming and expensive design spin. In contrast, Compliance Test Benches leverage the exact same industry-leading Compliance App used on Keysight Infiniium oscilloscopes. Compliance Test Bench mimics a real hardware test bench, and, using a scripting technology called “Waveform Bridge,” emits the same waveforms that the Infiniium app receives when you are testing in your lab. The new approach allows engineers to apply the same set of compliance tests in all three cases: real-time/on-scope, offline/on-scope, and offline/remote.


In Summary, Compliance Test benches can: 


Break the wall between Design Simulation and Lab Measurement

      • Exact same compliance software used for simulation and measurement


Provide probing point where it is not accessible inside the IC chip

  • Equalization takes place inside the chip for SERDES devices
  • It must be simulated to show if the data can be recovered by the receiver

Provide compliance validation before committing to hardware fabrication


Compliance test benches in Keysight ADS are virtual workspaces that can be customized for specific applications. Most of the connection in the design specification are included on these virtual workspaces. You can simply select them and run your simulation. Below is an example of the process to run a simulation to generate waveforms: 


Through this test, you can look at the host side eye diagram as well as the receiver side eye diagram and save the waveform results. Then you can run the exact same compliance application on the virtual scope that you have on your computer/machine. Now, at this stage when the simulation results pass the specification you can have confidence that there is an agreement between your pre-fabrication and post-fabrication results. This way if you find any inconsistency between the two results, you can target the specific problem area. 




More Information

You are designing a power amplifier and have a nonlinear device model. You may want to know what load gives the maximum power-added efficiency (PAE) while the device is delivering a specified output power and while it is operating below some maximum allowable gain compression. How do you do this? Andy Howard, a Senior Application Engineer at Keysight Technologies, has created a simulation example that will help you overcome this design challenge. 

The plots below show results in the Load_Pull_Using_Loads_From_File_Data_Mining data display. Andy has specified the desired output power of 32 dBm. The maximum allowed gain compression is increased from 2 to 3 to 4 to 5 dB. The PAE increases from about 49% to > 67%:

This example has two swept-power load pull simulations. Equations are used to interpolate the data to find the load that gives the maximum PAE while delivering a specified power while below a specified maximum amount of gain compression. One of the load pull simulations reads in loads you have specified graphically on a Smith Chart. The other load pull simulation allows you to specify a circular region on a Smith Chart.

To learn more, download Andy's swept-power load pull simulation example on Keysight EEsof Knowledge Center. (a login required)

Interested in Keysight ADS?  

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A statistical simulation technique has become popular for the design and analysis of high-speed signals. Especially where accurate prediction of random jitter is important, such as in the measurement of eye opening at ultra-low BERs. In this DesignCon 2017 paper published by my colleagues Hee-Soo Lee, Cindy Cui, Heidi Barnes, and Luis Boluna, you can learn about advantages of the statistical approach for the accurate prediction of random jitter at ultra-low BER, and the limitation of this approach due to SSN (simultaneous switching noise). This paper proposes a solution that extracts the mask correction factor from the voltage noise calculated from a transient simulation, then uses it for accurate prediction of eye height and eye width calculation in the statistical analysis. Measurement data is provided to validate the approach.


Crosstalk and Delta-I noise are significant noise sources for DDR4 designs and are known as simultaneous switching output noise (SSON), or SSN. For DDR4 systems (up to 3200 MT/s), the Inter-Symbol Interference (ISI) and Random Jitter (RJ) induce timing margin uncertainties, which cannot be ignored because the shrinking unit interval (UI). In order to take into account the RJ and ISI effects accurately, JEDEC introduced the new DQ receiver compliance mask at 1e-16 BER in the DDR4 specification.

The new DQ compliance specification requires an eye opening at an ultra-low BER level, 1e-16, which poses a new challenge to simulation-based design methodology. The traditional simulation approach was based on SPICE-like time domain simulation technologies.

As you may find from Figure 2, the eye shrinking induced by inter-symbol interference (ISI) and random jitter (RJ) is relatively small at a low data rate (800 Mb/s). However, the timing margin decreases by 9% UI (15ps) from 103 to 1016 bits because of ISI and RJ effects at 3200 Mb/s data rate system. This proves that time-domain simulation, even with several thousand bits, is far more inadequate to accurately predict the eye opening at 1e-16 BER level.


We can get the ultra-low BER contours at a fraction of the time required for SPICE-like time-domain simulation methods by using the statistical analysis method. The dilemma is that the statistical simulation has to be used for
calculation of the ultra-low BER contours but the Delta-I noise contribution for SSN is not taken into
consideration.To address this challenge, a practical and efficient SSN induced jitter and noise model extraction
method is proposed in this paper. The extracted jitter and noise values will be used to correct the
eye height and width calculation at a certain BER level as well as the JEDEC DQ compliance mask
to reflect the eye-margin correctly. This methodology improves the accuracy of DDR4 statistical simulation, by using the mask correction factor. The extraction process of mask correction factor is relatively simple and quick but still, delivers reasonable accuracy while overcoming the limitation of the statistical simulation approach with the SSN induced time variant Delta-I noise. The validated correlation between measured and simulated data as it is discussed in this paper proves that this methodology can be effectively used for DDR4 designs. 


If you want to learn more about a practical and efficient SSN induced jitter and noise model extraction
approach and the measurement process, download this 
DesignCon paper here: 

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Model Builder Program (MBP) is a one-stop solution that provides both automation and flexibility for silicon device modeling. MBP Script is a Java™ based scripting language, where no compilation is required at the user end. MBP Script runs equivalently on Windows and Linux. Many MBP-specific APIs(Application Program Interface) and high-efficiency programming structures are developed for Device Modeling work. IMV is the most commonly used process in MBP. Device Targets such as Vth, Idlin, etc are so called IMV in MBP, and are calculated from IV/CV data. The default BSIM4 IMV settings are shown below, we could see that many Device Targets, as well as their scaling plots have been created.


These device targets correspond to the IMV panel in the MBP main window, where all the IMV plots are displayed as long as the required IV or CV curves are loaded, as shown below.


Many IMV targets can be created without prior coding, since MBP Script provides many built-in algorithms and methods to create IMV targets such as, Idlin.


Double-clicking on Idlin opens the definition panel, as shown below:
Here, Idlin is defined as the Java Algorithm IMV Type, for all loaded devices, find Idlin as Current(Ids) from their Ids_Vgs_Vbs plots, where:

  • Vds = absmin(vds), meaning the absolute min Vds value from measurement data.

  • Vgs = absmin(vgs), meaning the absolute max Vgs value from measurement data.

  • Vbs = absmin(vbs), meaning the absolute min Vbs

    value from measurement data.

To specify the Restrictions, you could also directly assign a number, say Vgs=0; or, you could use a variable for flexibility, for example, Vgs=Vgg, where Vgg is a variable that must be defined in imv_const table, as shown below:

Script Editor

Many IMV targets can be defined like Idlin; however, if the logic is more than simply picking out a value from the IV/CV plot by a certain condition, you can use the Script programming.


For example, Gm, where derivative is used, as shown below:


MBP Script editor has Contents Assistance, Code Auto Completion, and C o l o r Coding functions to help ease and expedite your coding experience.
For example, the available function list to an object will drop down when typing the .(dot) sign. as shown below:


Another peek at the built-in Math functions:


MBP Script has an advanced step in debugging function. For now, we could use the old school Print() function to print out variables to the Message window.
To execute a Script file, simply click on the play button, as shown below:

Save and Reload

All the work we've done in MBP Script window can be saved as a single .zip file to a user defined folder. The zip file can be loaded back into the MBP Script window directly, no un-zip is required, which greatly facilitates your work for re-use, sharing and version control.


Use these 3 buttons on the toolbar to Save and Load, as shown below.
After you press Save to a current project, hit refresh, and as a result, all the changes will be reflected in the MBP main window. So newly created IMV plots can be viewed and used for simulation and optimization right away.
Don't forget to press dump or this icon to convert your project to a zip file, where it can be re-use and shared with all team members.  

Interested in Model Builder Program (MBP) Software?

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Say you are designing a power amplifier using a particular transistor. You have run load pull simulations on the transistor, possibly at different source frequencies. Is it possible to use this simulated load pull data to help determine which of numerous impedance matching network parameter values would give the best performance (satisfying gain, power, and PAE goals across a band of frequencies, for example)?

Andy Howard, Senior Application Engineer at Keysight Technologies, is demonstrating this technique with an ADS example.  By following Andy's example you will be able to specify the loads to be simulated by positioning two circles on a Smith Chart. When you are happy with the loads to be simulated, you activate an equation, and the loads are written into a text file. Subsequent load pull simulations read in the loads from the text file. Note that in order to plot the contours, you have to use Python. The Setting_up_Python_for_contour_plotting data display file walks you through the simple steps needed to install and configure Python.


Download Andy's ADS example from Keysight Knowledge Center (a login is required) to learn more:


Interested in Keysight ADS?  

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The Internet of Things (IoT) fulfills a promise of a more efficient and connected world. But with dozens of devices per household, battery management must become wireless and autonomous. This problem is now being solved through power harvesting, which enables a circuit to power itself from energy in the environment. This white paper discusses efforts from Ericsson and the University of Freiburg to develop wireless power of a couple of hundred nanowatts at 1V to power a sensor node. 

The challenge was to satisfy the impedance matching requirement when the antenna, resonator, and matching components were connected to the nonlinear load of the pair of Schottky microwave detector diodes, used as rectifiers. The ADS Harmonic Balance simulator was used to design the impedance matching circuit. Read the paper, “RF Energy Harvesting Design Using High Q Resonators” to learn more details about how Ericsson and Frieburg University designed a high Q power harvesting circuit using Keysight ADS.


Learn how ADS can help you in your power harvesting designs by clicking HERE for a free trial.

Every year, the top signal integrity, power integrity, and high-speed design experts present their insights and results at DesignCon. This year my colleague, Heidi Barnes, won DesignCon Engineer of the Year. Heidi is a Senior Application Engineer for High-Speed Digital applications in the EEsof EDA Group of Keysight Technologies. Below is the list of papers she authored for DesignCon2017: 

  • Accurate Statistical-Based DDR4 Margin Estimation using SSN Induced Jitter Model
  • Non-Destructive Analysis and EM Model Tuning of PCB Signal Traces using the Beatty Standard



You can now download these two papers, and all of the DesignCon 2017 technical papers featuring Keysight EEsof EDA authors here:

RF and microwave designs are usually sensitive to the physical dimensions of the layout. You can use ADS to vary dimensions and investigate performance. This workshop (that you can go through on your own) shows ways of parameterizing the physical dimensions of a layout so you can efficiently sweep or optimize them, even using EM simulations.

Here is a brief summary of what you will you be learning: 

  • How to automate ADS such that it will vary dimensions and/or location of objects in your layout
  •  How to vary the length of a line and separation between coupled lines of an edge coupled filter to optimize the response 
  • How to create MIM capacitor on GaAs which supports rectangular shapes, with any desired length and width  

Obtain the workshop material from the Keysight EEsof Knowledge Center (a login is required):

With increasing design complexity, RF designers now have to collaborate more closely within their RF design team in addition to contending with the challenges of interfacing with their fellow analog and digital designers. With designers located either locally or at remote locations sharing design data frequently and accurately becomes challenging and time-consuming. Moreover, with global teams, designers have to overcome the additional barrier of communication challenges to ensure smooth handoffs. Register to join Keysight Technologies and Qorvo Inc to learn how you can revision control within your RF design team while using Keysight ADS. ADS Free trial



When: Wednesday, February 1st, 2017 at 10.30 am PST
Duration: 30 minutes

Are you a Signal integrity engineer who may not have the time or budget to attend continuing education classes on the latest design tools and techniques? Here's a quick way to invest in your future and update your technical knowledge through these valuable webcasts streamed conveniently to your desktop. This free one-hour webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools for the purpose of optimizing the BER for highly pathological channels. Register for the Signal Integrity webcast now. 

For more information check out Keysight tutorials in Signal Integrity webcast library

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PAM-4’s ability to increase the data rate without having to enhance the hardware channel has significant hardware cost advantages. The new transmitter and receiver technologies are already showing viability for PAM-4 end-to-end links. To fully exploit the advantages of PAM-4 signaling my colleagues, Heidi Barnes & Fangyi Rao, have published a great article at Signal Integrity Journals on "Fast-Tracking Deployment in PAM-4 Applications with Commercially-Available Software and Hardware Tools".  From this article, you can learn in details how a new measurement and simulation eco-system must be established and validated to fast track deployment in PAM-4 applications. 

Try a free ADS 30-day trial.


You can now download Andy Howard, Senior Application Engineer at Keysight, updated example that shows different techniques for simulating the X-dB gain compression point of an amplifier or device (and that includes load pull.) The updated version now includes calculations of the X-dB gain compression using the small-signal gain as the reference, the maximum gain as the reference, and the gain at a user-specified available source power as the reference. You may download the example from the Keysight EEsof Knowledge Center (a login is required):

We have been hosting a one-day, hands-on Power Amplifier Workshop around the US. The workshop shows the use of ADS in the design of Class AB and Class E PAs, both of which use GaN devices. The workshop includes various load pull simulation techniques, optimization, ways of simulating X-dB gain compression, X-parameter model extraction, etc. The documents from the workshop as well as the workspaces may be downloaded from the Keysight EEsof Knowledge Center (Registered users only):

Harmonic balance is a frequency-domain analysis technique for simulating distortion in nonlinear circuits and systems. You can analyze power amplifiers, frequency multipliers, mixers, modulators, and many more designs under large-signal sinusoidal drive. Download the Harmonic Balance chapter from the ADS Example Book now.

See all of the chapters in the new ADS Example book.

Keysight EEsof EDA recognizes that its users are some of the best and brightest engineers in the world and we want to say thank you. If you’re planning on publishing a paper that references our EDA tools, then you’re eligible. See the eligibility requirements and fill out this short form to get your FREE “Distinguished Author” coffee mug as a gesture of our appreciation. See our growing list of distinguished authors.