Colin Warwick

Creating Verilog-A Models in ADS from VHDL-A Code: Part 2 - "All-in-one" Testbench

Blog Post created by Colin Warwick Employee on Dec 14, 2018

In my previous post, showed you how to create the Verilog-A code for a component model. In this post I'll show you how to import the code into ADS. If you don't have access to ADS or you're not familiar with it, I suggest you read our Quick Start Guide first.


There are two strategies for adding a model to an ADS workspace, let's call them "all-in-one" and "shared library" methods. "All-in-one" is the simplest and as the same suggests it is self-contained. "Shared library" is a bit more work to set up, but it saves time in the long run because you can reference the same library from each new project, and avoid having to recreate it every time.

I cover the all-in-one method in this post and the shared library in the next.

(Side note: There is also a further Verilog-A flow in the W2319 ADS RFIC Interoperability Element, but I won't be covering it in this series. If you are interested, the doc page is here.) 

All-in-one method

  1. Launch ADS. From the ADS Main Window menu bar, select File-->New-->Workspace
  2. In the "New Workspace" dialog box, give your new workspace a name such as all_in1_wrk 
  3. Click on the "Create Workspace" button.
  4. In the Main window "Folder view" tab, you will see a workspace folder whose name ends in ...\all_in1_wrk. Right click on it and select the last option in the pop up context menu, namely "Explore In File System".
  5. Assuming Windows OS, File Explorer opens in the workspace's folder on your file system. Right click on a blank space in the right panel and select New-->Folder. It is best to name the folder veriloga because then it will be on the default search path that the Verilog-A compiler looks in.
  6. Open your new folder and, using copy-paste and your favorite plain text editor, create the file containing the Verilog-A source code from Part 1. Name the file (The first part can be anything convenient, but the file extension must be either *.va or *.vams for the compiler to recognize it.) You can close your text editor and Windows Explorer if you like.  
  7. Go back to the ADS Main window and from its menu bar, select File-->New-->Symbol view...
  8. In the "New Symbol" dialog box, overwrite the default cell name (cell_1) with  resistor. Note that you are creating not only a view but also a cell. A cell is a container that holds one or more views of a component or a circuit. You never view or edit the cell directly but instead you view and edit it via one of its views. It is important that the cell name, resistor, matches the module name, resistor, in the Verilog code.
  9. In this "New Symbol" dialog box, click the "Create Symbol" button. Two new windows open: The Symbol Generator dialog box and the Symbol canvas itself.
  10. In the "Symbol Generator" dialog box, make sure you are on the Copy/Modify tab, then select "Lumped-Components" from the "Symbol category" drop down list. (Side note: if you want to use the Auto-Generate tab instead, you'll have to add an extra step to specify the number of pins. See Note 1 at the bottom of the this post.) Click on the resistor icon. The "Symbol name" edit box will populate as ads_rflib:R . Click OK to dismiss the "Symbol Generator" dialog box. By the way, you can draw your own symbol if there is no suitable one already: Search for the "Draw a Custom Symbol" topic in the doc.
  11. In the Symbol drawing canvas you can see the symbol as been automatically created, with pins 1 and 2 with default names P1 and P2. Double click on each pin in turn and change the name to match those listed in the Verilog code module resistor(p, n); i.e. set the name of pin 1 and 2, to p and n, respectively.
  12. From the Symbol window menu bar select File-->Design Parameters.
  13. In the "Design Parameters" dialog box's "General Cell Definition" tab, set the "Component Instance Name" to whatever prefix you want instances to have, R for example. Instances will be given default names R1, R2, R3, etc.
  14. Important! Uncheck the "Subcircuit" check box. (If you are curious, the difference between a subcircuit and a leaf node is that you can push into the hierarchy of an instance of a subcircuit, but not into a leaf node. Try it! Right click on any instance of a component in a schematic and select "Push Into Hierarchy" from its pop up context menu. If the instance is a subcircuit, the subcircuit will open. If not, you get a "Cannot push into this instance" error. This check box tells the netlister which type (subcircuit or leaf node) it is dealing with, so it can traverse the hierarchy correctly.)
  15. In the Simulation frame, select "Subnetwork" from the Model drop down list. (Wait a minute Colin, I thought you told me in the last step that what we are building is not a subcircuit? Well, it is isn't. It isn't a subcircuit, but it is a subnetwork. Yikes! A subnetwork is in contrast to a built-in component. The third option "Model" is for non-simulatable items like text annotations.) 
  16. Select the "Cell Parameters" tab of the "Design Parameters" dialog box. Remember the line parameter real r=0.0; in the Verilog code? Here is where you connect to it. In the Edit Parameter: Parameter Name edit box type r, leave the Value Type as "Real", set Parameter Type/Unit to Resistance, and type something helpful like "Resistance in ohms" for the parameter description. It is best to leave the Default Value blank. You can put a value in there, but it will override the default value in the Verilog-A file, which might be confusing if the two values get out of sync at some point. 
  17. Look to the left side of the same tab, and click on the "Add" button. The r parameter will be added to the parameter list box.
  18. Click OK to dismiss the "Design Parameters" dialog box.
  19. Go back to the "Symbol" window menu bar, and select File-->Save. We are done with this window, so you can close it if you like.
  20. Go back to the ADS Main Window, Folder View tab. Click on the little arrow to open your resistor cell folder. You can see that your cell now has one view: symbol.
  21. The next few steps prepares a testbench to instantiate it on. From the ADS Main Window menu bar, create a schematic view of a new cell by selecting "File-->New--Schematic...". This will be our top-level cell. Call this new cell "testbench."
  22. Arrange the Main window and the new testbench schematic window side-by-side.
  23. Click, hold, and drag your resistor symbol from the Main window's Folder view tab across your screen to the testbench schematic window. Instantiate your resistor by clicking anywhere on the testbench schematic canvas. Hit the ESC key to leave instantiation mode. Set the resistance to 2.0 ohms.
  24. Create a simple testbench like this:
  25. Click on the Simulate icon or select Simulate-->Simulate or just hit the F7 shortcut key. The first time you simulate, there is a short pause while ADS compiles the Verilog code. It saves the compiled model, so if you don't touch the code, there is no need to re-compile the next time you run it.
  26. From the Data Display window, insert a plot, and select the Vout and branch current (_ub_p_n_i) traces:
    voltage and current through 2 ohm resistor


The next posting, shows you the shared library method. A lot of the steps are the same, except we create separate workspaces for our component library and our test bench, and link the two.


Note 1: In Step 10 above, if you want to use the Auto-Generate tab instead of the Copy/Modify tab, you'll have to add an extra step to specify the number of pins. Create a schematic view in the cell you are working on, then place one pin for every port in the Verilog-A function argument list e.g. 2 pins for module resistor(p, n); . It looks odd to have a schematic with nothin but unconnected pins, but trust me it works! Then save the schematic and go back the symbol view Auto-Generate tab.