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2018

Keysight EEsof EDA’s Advanced Design System (ADS) software can help you overcome your signal and power integrity challenges. As the world’s leading electronic design automation for RF/MW and high-speed digital applications, ADS features a host of new technologies designed to improve productivity, including two EM software solutions specifically created to help signal and power integrity engineers improve high-speed link performance in PCB designs. 

Below are ten ways ADS can solve your most common SI/PI Design Challenges.

 

1. ADS provides speed and accuracy for your SI EM characterization

Don't be slowed down by increasing data rates. ADS provides two EM analysis solutions - SIPro and PIPro - that are specifically designed to handle high data rates, without sacrificing accuracy or speed. The limiting factor of 3D-EM technology for SI analysis is simply the scale and complexity of PCB designs. However, SIPro focuses on enabling SI EM analysis of high-speed links on large, complex high-speed PCBs, while PIPro is used for PI EM analysis of power distribution networks, including DC IR drop analysis, AC PDN impedance analysis, and power plane resonance analysis. 

 

Figure 1. SIPro delivers results approaching the accuracy of full-wave 3D-EM solutions, but in a fraction of the time.

 

2. ADS simplifies the use of S-parameter files for your parts

Imagine you’ve just downloaded an S-parameter file for a part you are considering; in this case, a high-speed connector for a backplane. It has a large number of ports on it, so you want to first inspect the quality of the data and then use it in your simulation. How do you wire it up? Which ports are paired?

Traditionally, the answer might be to open up the data in a text editor. However, with ADS’s S-Parameter Checker, designers can now easily view the contents of any S-parameter file without having to setup an S-parameter test bench simulation. This allows them to directly plot the individual relations they wish to see, and shows them the port names against each pin. It also tells designers if the file is passive or reciprocal, as well as the number of data points in the file and the frequency range it covers. Designers can even use S-Parameter Checker to rename, re-order and reduce the number of ports, which enables them to save a new, more usable S-parameter file (Figure 2).

 

 

Figure 2. The S-Parameter Checker allows design engineers to easily rename, re-order and reduce the number of ports.

 

3. ADS provides access to industry-leading channel simulator technology

ADS's channel simulator technology sprung forth in 2009 when transient simulation (SPICE) couldn’t address the measurement of margin-to-mask for really low bit-error-rates (BER), as demanded by high-speed link designs.

Dr. Fangyi Rao's 2006 patent to correct for passivity, while ensuring causality, ensured ADS to be regarded as the msot accurate solution for handling cascades of S-parameter models combined with circuit models in one schematic. The pace of innovation continues today with ADS's Channel Simulator still the industry-standard model. Additionally, the Channel Simulator now supports IBIS package (.pkg) entries directly and more extensively before.

 

Figure 3. With ADS, designers can mix-and-match models from IBIS, IBIS-AMI, SPICE, and generic built-in models.

 

4. ADS stays ahead of technology waves (such as PAM-4)

Market pressures on IP routers set an expectation to do more at a lower cost per bit. However, to go faster and provide a single 100-Gbps electrical lane across the distance of a typical backpane is beyond present day technology. 

The solution lies in Pulsed-Amplitude Modulation (PAM) for high speed serial links. PAM represents a revolutionary step in the industry, but comes with its own unique set of challenges as well. For example, we can transmit a PAM-4 symbol at 28 Gbaud and deliver 56 Gbps at the other end, but the IC's use more power and the signal itself has a reduced Signal-to-Noise ratio (SNR). 

Whether you are challenged with managing complexity while reducing production cost, or researching how to go further and faster on low-loss materials and fabrication processes,

 

 Figure 4. ADS supports PAM-4 simulations, which offers a viable alternative to NRZ. 

 

 

5. ADS accelerates DDR4 simulation methodologies

In simulations, how do you check compliance against the mask? Keysight EDA offers a novel DDR Bus simulator specifically designed to accomplish this task. It is a bit-by-bit channel simulator for parallel buses. It characterizes all transmitter paths at once, and calculates the BER contours for each eye at the receive side, together with the measurements for margin to mask. 

The simulator is unique in that it correctly handles the asymmetric rise and falling edges found with single-ended signals.The Tx and Rx models can be used to drive IBIS models, or mixed with SPICE models. The speed of the simulator allows it to be used in place to transient simulation for many pre-layout tasks, where the designer wants to sweep multiple parameters, or investigate performance movements. Together with batch simulation, it is a powerful tool for pre-layout design exploration, as well as post-layout verification for compliance.

 

Figure 5. Keysight EEsof EDA's DDR Bus simulator is a bit-by-bit channel simulator for parallel buses.

 

6. ADS puts power in the hands of designers

Power Integrity has become an ever-increasing challenge in modern day high-speed systems, driven by three main forces: higher device integration, lower IC supply voltages, and smaller real estate on the PCB. These modern challenges have forced engineers out of their notebooks and into true PI-DC simulators in order to take into account the real physical layout of the power delivery network (PDN). 

With ADS and the new PIPro suite of EM simulators, designers receive visual feedback in just second on exactly what the voltage distribution looks like for the selected power and ground nets. ADS also allows designers to check the current flow through individual vias and the voltage and current at specific locations like individual pins on the sinks and voltage regulator module (VRM). This information is easily reported in a sortable table. Vias that carry too much current can be highlighted in the layout for easy identification (Figure 6).

 

Figure 6. Vias carrying too much current can be highlighted in the layout for easy identification.

 

7. ADS enables flat PDN impedance responses

Once the initial pre-layout design has been created, the first-pass of the PCB layout can be imported into ADS 2016 for analysis using PIPro EM technology. PIPro’s net-driven user interface allows designers to quickly select the power and ground nets for the PDN network they want to simulate, choose simulation models for each of the components (e.g., decaps, EMI filters, inductors, and resistors, etc.), and setup the PI-AC simulator to compute the PDN impedance of the distributed layout with components in place. 

Since the PI-AC simulator has EM technology designed specifically for this purpose, a very accurate result is returned in minutes, not days. Designers can then use ADS 2016’s field visualization, PDN impedance and S-parameter plotting to determine if there are problems with the current PDN design, and to check coupling from one capacitor to the next. With just one click, a schematic representation is generated to transfer the EM-characterized model, together with circuit models of the components.  This back-annotation to an ADS Schematic enables  one smooth cohesive workflow. Designers can then apply their behavioral VRM model, and further tune the decaps for final verification/optimization.

 

Figure 7. Increasing the decoupling capacitance while increasing ESR improves impedance response flatness.

 

8. ADS enables electro-thermal simulation

As power delivery networks are forced into tighter PCB real-estate, the power plane becomes far from idealized.  Usually the once perfect plane is perforated heavily with clearance holes from stitching vias, and it can be a struggle for the layout engineer to get the required current up into the package of the device that requires it, without passing through narrow traces of metal.  Calculating an accurate IR-Drop is important for the PI designer, but also knowing the absolute temperature that the PDN traces, vias and chip die will reach, is invaluable information.   High temperatures can cause reliability issues; as the temperature cycles from on/off states can cause the via barrels to weaken and crack over time.

It is not intuitive to the designer whether a via is undersized for the current that is passing through it.  The temperature rise is very dependent on the width of the traces attached to it.  Secondly, resistance of a trace increases with temperature, requiring simulation analyses to determine the final steady state condition.  For every 10 degC change in temperature we see a 4% change in resistance of a trace. These observations point to a need to simulate the PDN design with a DC IR Drop electro-thermal solution.    

ADS provides a fully-automated integrated Electrical-Thermal-Electrical iterative simulation.  Users receive the most accurate representation of DC IR Drop results by taking into account local resistivity changes due to heating. The additional Thermal-only simulation, gives the user the ability to perform thermal floor planning.

With ADS you can easily copy existing DC IR Drop simulation setup to new Electro-Thermal simulation and visualize a list the temperature of planes, pins and vias.

 

Figure 8. DC IR Drop Electro-Thermal analysis - visualization of temperature.

 

9. ADS has an interconnect toolbox (Via Designer and CILD)

The signal integrity design challenge is not just to successfully recover the transmitter signal at the receiver, but to understand what is controlling the performance.  What are the significant margin eaters and which ones can I optimize?

Typical connections between a transmitter and a receiver include some section of application specific custom PCB routing.  ADS has a signal integrity tool box to help explore the design trade-offs and deal with the complex interaction between stack-up, transmission line losses, and via topology.

Designing the PCB interconnect starts with some sort of PCB stack-up definition in order to start evaluating the different types of possible transmission line topologies.  Once the transmission lines are optimized for impedance and losses, then one needs to look at via performance to transition between layers. Anyone of these steps has cost and performance trade-offs that can impact the other, resulting in a complex inter-relationship to determine which feature is the real margin eater:  Layer Count, Line Z, Via Backdrills, Material, Layout Density, etc.

ADS provides an Interconnect Tool Box that includes Substrate Editor, Controlled Impedance Line Designer, and Via Designer to simplify the pre-layout PCB interconnect investigation.

Figure 9. This type of pre-layout investigation enables an engineer to understand what is controlling the design margins and make informed cost vs. performance decisions.

 

10. ADS embodies the Keysight philosophy:

Hardware + Software + People = Insights

With Keysight's greater software-centric solutions focus, Keysight EEsof EDA plays a leading role in virtual compliance testing. Through Compliance Test Benches in ADS, designers can now take ADS simulated waveforms and test them against the same gold suite of compliance tests used on the bench with final verification hardware to attain the utmost confidence in a designs's compliance.

Further bolstering these capabilities in ADS is the support Keysight EDA offers its customers. That support includes a world-wide technical support presence, expert Application Engineers and consultative Field Sales Engineers. This support, together with Keysight’s hardware and software solutions and technical expertise gives customers greater insight and in turn, greater chance of success.

 

 

Keysight ADS further cements its leading position in electronic design software with continued advances for circuit simulation, layout and layout verification, silicon RFIC, and just as critically, signal and power integrity.

 

Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity. Find other cool posts here!

 

Last time on Tim’s Blackboard, we talked about linear Feed-Forward Equalization (FFE). This week, we will discuss the nonlinear Decision Feedback Equalization (DFE).

 

All the ADS content shown is in the attached workspace. Make sure you download the attached workspace and apply for a free trial to apply DFE to your own channel!

 

Introduction

When I first learned about decision feedback equalization, one of the bullet points is, “it is a nonlinear equalizer”, but I never knew why. Today, I will answer the question:

What makes DFE a nonlinear equalizer? 

Decision Feedback Equalization Technique

Shown in Fig. 1, decision feedback equalizer (DFE) can open a closed eye. Nonetheless, the signature of an opened DFE eye is different than other equalizations. There are kinks in the eye diagram. To examine the eye diagram a little closer, we apply single pulse analysis to look at the blink of an eye.

 

Fig. 1: Keysight ADS channel simulation demonstrating Decision Feedback Equalization (DFE) with different number of taps. DFE exhibits kinks in the eye.

 

Just like the eye diagram, we expect the single pulse response after decision feedback equalization to also have kinks. Sure enough, in Fig. 2, we see the kinks in the equalized single pulse response.

 

Fig. 2: Equalized single pulse response shows how DFE corrects post-cursor ISI on a single pulse that has all 0’s but a single 1. DFE inserts negative amplitudes after the received “1” pulse to better detect the next 0.

 

Taking a closer look, one observes that since the single pulse has all 0’s but a single 1 in Fig. 2, as soon as DFE algorithm sees a 1, it tries to reduce inter-symbol interference (ISI) by adding negative amplitudes so that the following low voltage is lower, allowing better detection of the next 0.

 

By the same token, when we send a single pulse that has all 1’s but a single 0, we should expect that as soon as the algorithm sees a 0, it tries to reduce ISI by adding positive amplitudes, allowing better detection of the next 1.

 

Fig. 3: Equalized single pulse response shows how DFE corrects post-cursor ISI on a single pulse that has all 1’s but a single 0. DFE inserts positive amplitudes after the received “0” pulse to better detect the next 1.

 

Result shown in Fig. 3 is consistent with our expectation. DFE algorithm is reducing ISI based on the detected data (symbol).

 

Fig. 4: Comparison between received waveform and equalized waveform shows how DFE acts on the received waveform.  

 

By comparing the received waveform and waveform after DFE, as seen in Fig. 4, we can further see the action of DFE algorithm, but the question remains:

What makes DFE a nonlinear equalizer?

Symbol Detection and Decision: A Nonlinear Filter

At the arrival of received data (symbols), DFE algorithm detects and makes a decision. Assuming the decision is correct, proper tap values are chosen and feedback to the originally received data.   

 

Fig. 5: An example of a symbol detector. Because the output does not scale linearly with the input, a symbol detector is nonlinear.  

 

Shown in Fig. 5 is a symbol detection processing block. As the input doubles from 0.6 V to 1.2 V, the output does not double. Consequently, symbol detection is nonlinear. In turn, decision feedback equalization is also nonlinear.

But how do we make sure the detection is correct?

Fig. 6 is an illustration of DFE block diagram. The received symbol first undergo feedforward equalization so that the symbol detector can make the correct decisions. After the symbol detector makes a decision, the result goes through a feedback filter to be combined with the previously detected symbol.  

 

Fig. 6: Decision Feedback Equalizer (DFE) block diagram. A feedforward filter is at the front end of DFE to help the symbol detector make a correct decision. Each decision then goes through feedback filter to be combined with previous symbol.

 

Because the input to the feedback filter consists of the sequence of decisions from previously detected symbols, which it uses to remove the portion of the ISI caused by those symbols, DFE only removes post-cursor ISI. Moreover, since DFE assumes that past symbol decisions are correct. Incorrect decisions from the symbol detector corrupt the filtering of the feedback loop. As a result, the inclusion of the feedforward filter on the front end is crucial in minimizing the probability of error [1].

 

Realization of Decision Feedback Equalization

Given the basic algorithm of DFE, I decided to design my own DFE, see Fig. 7.

.

Fig. 7: Demonstration of a homemade DFE in Keysight ADS. See attached workspace for detail.

 

Knowing the input sequence is going to be a single “1” pulse, i.e. all 0's but and single 1, I first changed the feedback filter coefficients, V_tap1 and V_tap2, until the post-cursor ISI is reduced enough. Then, I adjusted the delay of the two taps so the corrections take place at the right time. When all was said and done, I had created a homemade 2-tap DFE. Fig. 8 shows the equalized single pulse response.

 

Fig. 8: Applying homemade 2-tap DFE to a single pulse.

 

In the process of creating a homemade DFE, I learned that DFE algorithm is not trivial. It requires many moving pieces to align. Besides the correct symbol detection, the timing and feedback filter coefficients (tap values) also need to be appropriately selected for different channels.

 

Fig. 9: DFE algorithm is readily available in Keysight ADS channel simulation. There are several adaptive algorithms to choose from.

 

Good news! To help expedite the simulating and testing process, DFE algorithms are implemented and readily available in ADS. ADS helps you test the amount of stress your channel can handle with DFE and adaptive DFE enabled, see Fig. 9. 

 

Summary of Equalizations

After today, we have talked about all three equalizations,

·        Continuous Time Linear Equalization (CTLE),

·        Feed Forward Equalization (FFE),

·        Decision Feedback Equalization (DFE).

 

Below is a summary of the equalizations.

Table 1: Summary of Equalization Techniques 

 

Each of the equalizations has its own personality. While CTLE is sitting in the analog world, operating in the frequency domain, in the digital realm, FFE and DFE are working comfortably in the time domain.

 

Of course, each personality has its strength and weakness, and so does each equalization. In the near future, I will examine the pros and cons of equalization techniques. Make sure you bookmark the blog and check back regularly.    

 

For the upcoming post, I will take a step back and ask the question:

What is Signal Integrity? 

Until next time, make sure you download the attached workspace and apply for a free trial to apply DFE to your own channel!

 

References

[1]       S. H. Hall, Advanced signal integrity for high-speed digital designs. 2009.

 

kaelly_farnham

What is PathWave?

Posted by kaelly_farnham Employee Feb 14, 2018

PathWave is the new design and test software platform from Keysight Technologies. It combines design software, instrument control, and application-specific test software in an open development environment.

 

PathWave was the big news that Keysight unveiled at DesignCon.

 

PathWave at DesignConPathWave design and test software platform

PathWave signs were all over the DesignCon floor and meeting rooms. PathWave is an open, scalable, and predictive software platform that integrates hardware and software at every stage in the product development workflow. The PathWave software platform provides you with flexible and immediate access to the design and test tools you need, when you need them. 

 

Kaelly delivers flash seminar at DesignCon

 

At the show, I delivered a Flash Seminar about PathWave that was standing room only. Customers were very excited to hear how this new platform will affect them. It will help all engineers who work in design and test save time by connecting and integrating their workflows.

 

How does PathWave save me time? This was the most common question I got from engineers at the show.

 

The PathWave platform is built on a software framework that will connect all software and hardware in design, test, measurement, and analysis. On top of the framework, PathWave offers plug-ins and applications, enabling engineers to customize the environment for their specific tasks. It’s the customization combined with the interoperability provided by the common framework that allows for the most time savings. Below is an example.

 

 

PathWave Semiconductor Manufacturer Example

PathWave will connect and integrate the entire design and test workflow as shown in this example of a test setup for a semiconductor manufacturer.

 

PathWave can be customized for many applications, and above is just one example of a semiconductor manufacturer who needs to save test time because they are missing production targets. This customer struggled because they had a growing number of test parameters, were spending too much money on separate software test modules, and had a complex architecture that wasn’t easy to develop in, visualize data flows, or debug.  

 

With Keysight PathWave, their entire workflow will be connected and integrated with one single platform.  If desired, they’ll automatically get updates for all new releases of the software. They can save even more test time by pushing all the computations to the cloud or a local cloud. They’ll be able to connect to 3rd party hardware, so they can connect to existing equipment they already have. They can choose a software environment that includes a lightweight sequencer, plugin templates, package manager as well as development GUI, results and timing analyzers for best test team collaboration and efficiencies.  They can rely on consistent measurements from early validation to final manufacturing. 

 

And with Analytics as a big part of PathWave, they will be able to gather, store, and perform analytics on their test equipment and manufacturing data, improving productivity and asset utilization with the built-in predictive algorithms.

 

This is just one example of how PathWave is saving engineers time. For more information, check out PathWave online or contact Keysight.

Phased Array Systems have been around for decades, mostly confined to the aerospace industry; but with 5G development underway, phased arrays are becoming more common and in demand. In order to successfully design and deploy a product the first time, engineers should know how to avoid costly mistakes by using new techniques and simulation methodologies.

 

Mistake 1: Not predicting the far field spurious emissions in the simulation.

Whether you have an Aerospace/Defense or a commercial communications system, it must pass the test of a spurious emission mask (SEM). The masks are specific to each application, but the requirement remains the same. In the case of phased array, due to the added spatial dimension, the SEM test is more elaborate and is conducted in an anechoic chamber. The SEM test is conducted over the entire sphere (4π solid angle) for all the desired beam directions in both azimuth and elevation.

 

This very laborious procedure will be repeated if the spurious emissions are found the first time in the chamber and then have to be corrected in the design and brought back to the chamber. Therefore, if one can predict them upfront in the design cycle, the time spent in the anechoic chamber can be greatly reduced.

 

Figure 1. Predicting the desired beam directions up front in the design cycle, the time spent in the anechoic chamber can be greatly reduced.

 

This video goes into detail about how these spurious emissions can be predicted.

 

Mistake 2: Failing to explore the design thoroughly in the simulation phase.

Why would anybody not explore the design and simulation space?  There can be many reasons, but most likely it's due to the simulation speed and the accuracy of the modeling tool. One troubling behavior of phased arrays is coupling between the elements. The cost of a phased array is directly proportional to the size of the array. It is tempting to reduce the inter-element spacing, but unfortunately, that leads to increased coupling between the elements.

 

The coupling can happen in a few ways. If the lines in the feed network are close, they get coupled. An element not only transmits but can also potentially receive the energy from the adjacent radiating elements. This appears as the reflected energy back into the element’s input.

 

A third mechanism can also happen; if the elements are realized on the same substrate, higher order surface modes can be excited, propagated, and ultimately radiated. All these effects might cause loss of directivity in certain directions called blind angles. Unless one models the coupling effects and impedance mismatches accurately and explores the design over all the scan angles, these blind spots cannot be uncovered. A typical simulation shows a mild form of loss of directivity shown in the figure below.

 

Figure 2. Antenna coupling can cause loss of directivity in certain directions, called blind angles.

 

Mistake 3: Relying on simple spreadsheet calculations.

It is very popular to use spreadsheets to design RF systems. While it is true that they are readily available and quick to simulate, spreadsheets lack the capability to model and simulate. They cannot model multi-ports, RF mismatches, finite isolation, frequency response, accurate non-linearity, collated or uncollated noise, etc.

 

These common limitations become severe limitations when you start designing phased arrays. You need insights into all the paths, and phased arrays can have up to 400. You need to look into all the 400 paths to understand the behavior; because in a phased array, you cannot simulate one page and scale it up to 400 paths. You need to consider all of them simultaneously to achieve accurate results.

 

Figure 3. Phased array system design is much more complex than a single path RF system design. Designers cannot scale up the analysis of a single RF path analysis to a full array.

 

Under certain conditions, the amplifiers in the array are compressed. Due to this compression, the spurious radiation is violating the SEM as shown in the figure below.

 

Figure 4. SystemVue helps designers catch spurious radiation that violates the spurious emission mask, and can identify which amplifiers are driven into compression or saturation.

 

That's because some of the amplifiers in some of the chains are being driven into compression or even saturation. So how do you identify these amplifiers? Modern tools, such as SystemVue, make it easy to identify them and understand where the non-linearity is coming from.

 

 

Modern design simulation and modeling technologies will make it easy for engineers to avoid these costly mistakes. Watch Keysight’s latest video, How to Avoid Costly Mistakes in Designing Phased Array Systems, to receive greater insights on how to work around these common errors and download the workspace he uses in the video.

 

 

 

 Start your free trial of SystemVue today!

 

 

 

 

 

ICCAP - External Simulator interface

 

IC-CAP is a tool that enables modeling engineers to extract device model parameters using the simulator of their choice. For each model parameter extraction, measured data is compared against simulated data, and parameters are optimized to achieve the closest fit to the measured data. Because different simulators may use different syntax or "templates," adding a new simulator that is not supported requires its output to be adapted to one of these templates. For example LTSpiceIV uses a syntax that is very similar to SPICE3. IC-CAP supports the following simulator syntax:

  • SPICE2
  • SPICE
  • HPSPICE
  • HSPICE
  • Eldo
  • SPECTRE443
  • spicemodeads
  • SmartSpice
  • spmodeads
  • SPECTRE
  • Saber
  • hpeesofsim (native ADS syntax)
  • spmodeads (Spectre syntax)
  • hspicemodeads (Hspice syntax)

 

To make a link between IC-CAP and some external simulator, one must edit the config file $ICCAP_ROOT/iccap/lib/usersimulators.

usersimulators

 

In this config file, every line represents instructions on how to connect a different simulator to IC-CAP. The format is presented as follows:

simulator_name template_name path_name host_name pipe_capability

If the hostname is blank (or ""), then we assume the simulation will run on the same computer as IC-CAP. Some example entries are shown in the usersimulators file below.

usersimulators example file

Note: Lines with leading # sign are comments.

 

To link to an external simulator, the steps are as follows:

  1. Install the simulator program, making note of where the binary executable file resides. Also, verify that you have a valid license.
  2. Append or edit the entry in the $ICCAP_ROOT/iccap/lib/usersimulators config file for the external simulator in question.
  3. Re-start IC-CAP.
  4. In the model file where the simulator is to be used, specify the SIMULATOR variable to that simulator's name defined in the usersimulators file.

 

Troubleshooting

Should you encounter any problem, please try the following procedure, as it will usually allow you to figure out the problem. If that doesn't work, simply collect information from the steps in this procedure, as well as any pop-up error messages, and send it to the IC-CAP support team.

  1. Turn on IC-CAP's Status window, and check to see if any warning or error message appears.
    Illustration on how to bring up status window.

  2. Further, turn on the Simulation Debugger window. Check the netlist created by IC-CAP and the simulator's output files.
    how to get simulation debugger from IC-CAP

Note: Once the problem is addressed, it's recommended that you close the Simulation Debugger window. Leaving it open will slow down the overall simulation speed due to additional input/output interaction.

 

Using this process, you can quickly and easily link IC-CAP to a supported external simulator.

 

ShuangCai