Colin Warwick

Transphorm Manages Layout Parasitic Effects Using ADS

Blog Post created by Colin Warwick Employee on Aug 2, 2017

This Case Study highlights work published in a recent paper in IEEE Power Electronics Magazine entitled Utilizing Modern Design Methodologies for Wide-Bandgap Power Electronics by my colleague here at Keysight EEsof EDA, Chris Mueth, and by Rakesh K. Lal of Transphorm, Inc. The high di/dt and dV/dt edges in switched-mode power supplies (SMPSs) combined with layout parasitics can create unwanted voltage spikes. The authors demonstrate that EM-circuit co-simulation can predict these effects. With the insights from this predictive tool in hand, they rapidly explore the design space and mitigate the impairment. The time and money spent on board spins is reduced and the time to market improved.

The Challenge

Since GaN switches are intrinsically very fast, one can have a very high change in voltage versus a given change in time (dv/dt) (>300 V/ns) and a change in current versus a given change in time (di/dt) (>5 A/ns). So, designers need to use good design practice for high-frequency layouts. Three cardinal rules that apply are:

  • Minimize capacitances to ground or other nodes at high dv/dt nodes to minimize Ispike = C dV/dt
  • Minimize parasitic inductance in high di/dt branches to minimize Vspike = L di/dt
  • Guard or shield high-impedance signal nodes, such as the gate of a drive transistor with appropriate guard rings and shields.

Physical prototypes are costly and time consuming to build and don't give insight into details like current crowding (which is indicative of excess inductance). But virtual prototyping in a tool like ADS (which allows EM circuit co-simulation) do exactly this. 


The Solution

The authors used ADS to gain insight into design weaknesses. The key point here is that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along with the effects of the layout. You can plot the voltage spikes and do "what if..." design space exploration, such as using a ground plane for the return current, to minimize their effects.


The Results


The Transphorm reference design analysis used the Momentum method of moments EM field solver. The EM-model extraction took roughly one hour. The tool automatically creates the components representing the layout from the port-to-port network parameters generated by the EM field solver. The analysis tool then simulated the circuit schematic including the extracted model in the time domain.


After experimenting with various "virtual prototypes", the final reference design utilized two power planes, which were poured onto two different PCB layers. This provided the best possible reduction in power plane inductive parasitics. In addition, the power planes were placed close together and provided an additional capacitance benefit. As a best practice, the ground layer was located under the main trace routing layer to provide additional capacitance to help reduce the stray inductance of these traces. 


The reference design produced an efficiency of 98.5% for the buck half-bridge configuration. This correlates well with the 98.3% efficiency seen in the simulation. The gate-driver waveforms also correlated well.


Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!


Best regards,

-- Colin


PS Here's the link to request an ADS evaluation license if you want to try it.