The trend in switched-mode power supplies is to use wide band gap devices because these enable a higher switching frequency and higher edge speeds (the “di/dt” of the switched loop). These two in turn enable a smaller, lighter, cheaper power supply because the energy storage capacitors and magnetics can be smaller if you top them off more frequently. The higher edge speeds enable higher efficiency because there’s less heat dissipated when you have lower switching losses because the transistors spend less time in the dissipative cross over region.
These high slew rates come with a dark side, in particular the large spike voltage and noise generated by the layout parasitics, particularly inductance, of the PCB layout traces. This phenomenon is often called conductive electromagnetic interference (conducted EMI).
My colleague, Andy Howard, talked about how to deal with this a while back in his video entitled “How to Design DC-to-DC Power Converters”, but a frequently asked question was “When should I start to worry about layout parasitics inductance? Is there a quick rule of thumb that says kind of ‘Caution: Further investigation’s needed?’” The answer is "Yes!" and this follow up video is about how to make these estimates. Here's the link: