MichelAzarian

GoldenGate 2017 Adds Safe Operating Area (SOA) to the RFIC Designer’s Arsenal

Blog Post created by MichelAzarian Employee on Apr 6, 2017

Introduced in a separate post, GoldenGate 2017 enhances circuit reliability in RFIC design by checking against electrical (such as voltage and current) and geometrical rules that exist in the PDK and/or rules set by the user. This feature is referred to as safe operating area, or SOA. When GoldenGate 2017 finds out that one of these rules is not met, it will issue a warning in the log file. The RF designer can also track down the failing device(s) in the schematic with the tool’s highlighting feature for an efficient debugging experience.

In analog and RF circuits it is common, for instance, to have different voltage and FET domains, making it easy to have a higher voltage being allowed at some nodes but that same voltage being destructive at other nodes. Traditionally, the check for overvoltage is done manually, which, of course, is not generally reliable and is tedious. The simulation tool can perform this task much more efficiently.

Here is an example where the drain of the transistor sees a slight overvoltage that is not high enough to damage the transistor right away, making the oversight hard to uncover during chip evaluation. However, ignoring this slight overvoltage will cause reliability issues down the road, the type that gives semiconductor manufacturers nightmares. GoldenGate 2017 eliminates these fears. It checks against PDK rules by reading the asserts in the kit and it also allows the user to set his or her own rules to check against, enhancing overall reliability.

GoldenGate 2017 integrates the SOA functionality in a well-designed fashion, making it efficient for RFIC designers to check against rules. Besides printing assert violations in the simulation log file, GoldenGate’s “Violation Display” GUI makes the management of rule violation a breeze by displaying a summary of rule checks. Further debugging is straightforward and is done by expanding the details in the same window. Highlighting the violating device(s) in the schematic is also possible at this stage with the click of a mouse button.

Furthermore, results from sweep runs can be expanded into a separate display window for convenient study and comparison. The tables dynamically update column entries to include only relevant data and to keep the table size manageable.

Do you work on RFIC design and have not tried GoldenGate yet? Download your free trial and discover how this world-class circuit simulation tool can help optimize your design process and resolve your circuit simulation challenges.

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