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Looking For A Way To Ensure High Signal Quality In PCIe Gen3 Serial Channels?

Blog Post created by kaelly_farnham Employee on Mar 23, 2017

PCI Express Gen3 (PCIe Gen3) specifies a high-speed differential I/O interconnect that runs at 8.0 Gbps. It has many benefits, and it also presents a critical challenge. PCIe, using high-speed 8-Gbps serial links, can suffer from a large array of physical phenomena and this can lead to excessive EMI emissions in large systems. Fortunately, there is a way to overcome this challenge and ensure high signal quality in PCIe Gen3 serial channels. The solution involves the use of signal integrity analysis, compliance testing, and a PCIe interface simulation methodology that relies on IBIS-AMI models to account for different channel parameters—all of which can be accomplished using Advanced Design System (ADS) software (Figures 1 and 2).

 SI analysis, PCIe Connector, PCIe Gen3, eye diagram, Keysight ADS

Figure 1. During SI analysis, the PCIe connector, 8-lane data bus and package are simulated using an EM solver. S-parameter data is then extracted and factors like impedance matching and propagation delay are analyzed. Finally, all data is re-combined and a Pseudo-Random Bit Sequence (PRBS) is generated at a bit rate of 8 Gbps. The simulation setup and result of a transient analysis with PRBS random data input for the channel is shown here.

 

PCIe channel, PCIe 3.0, Keysight ADS

Figure 2. Compliance testing ensures products are interoperable. It validates that the PCIe channel is compliant with the PCIe specification. Shown here is the eye and jitter measurement in ADS on a PCIe 3.0 transmitter transaction bit.

 

Want to learn more about this approach and what it entails? Check out the article, Ensuring High Signal Quality in PCIe Gen3 Channels, by Keysight Technologies’ Anil Kumar Pandey in the Signal Integrity Journal.  

 

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