2017

January 2017

# Transconductance Modeling for Low-Power Design

Posted by rajsodhi Jan 18, 2017

Engineers are constantly being challenged to work at lower supply voltages that are now on par with the threshold voltage of the device itself. For design successes in microprocessors, transceivers and mobile devices, it becomes imperative to accurately model CMOS transconductance (Gm) and threshold voltage (Vth). In our December 2016 newsletter, we described different ways to define the Vth of a transistor. Today, we will explain how to extract Gm near Vth using Keysight’s Model Builder Program (MBP) in 3 simple steps.

1. Access your previously calculated Vth, and define your target Vgs relative to Vth.
2. Look up or interpolate the derivative of Id with respect to Vgs at your target Vgs
3. Expand your analysis of Gm to observe how it scales with respect to device width and length.

Transistor transconductance, Gm, is defined as the derivative of output current with respect to input voltage:

Gm = d(Iout)/d(Vin) given a fixed Vds and Vbs (50 mV and 0 V, for example)

This has special significance in CMOS modeling, because almost all the amplifier gain is a function of transconductance of a MOSFET.  Hence it is one of the most important measures of a device.

On a single device, we control Vgs, Vds and Vbs and measure current Ids or Id.

An IV graph (Ids vs. Vgs) of a transistor is shown below at Vds = 50 mV and at a range of Vbs.

Let’s go through each step described above.

Access your previously calculated Vth, and define your target Vgs relative to Vth

InterMediate Variables (IMV), as the name implies, are bridging variables between the raw data and the final device model parameters.  We may look to see how Vth and Gm evolve over temperature or across device geometry, and then capture these behaviors in our model.  As shown below, Vth and Gm are included in BSIM4 default IMV settings.

Since small signal characteristics like Gm depend on device operating point, it becomes helpful to choose an operating point.  Circuit designers may look at Gm at a point just above the threshold voltage.

Vgs = Vth + deltaVg

Let’s define deltaVg as our parameter of interest, say 0.1V.

Because we are going to use a variable called "deltaVg", we need to define it in a table of intermediate variable constants called “imv_const.”

Next, we’ll create a new intermediate variable called “GmNearVth.”

Run the command New -> IMV.

Edit the IMV definition to reflect the following:

 Page Name: imv.imv.gm, input data, because we eventually want to get a Gm value. Restrictions: device,vbs,vds Algorithm Class: acc/GetValueAtPoint means simply look up the Y value at a chosen X. Attached Targets: Vth, this is how we pass in another IMV Target. Algorithm Parameters: gm,vgs,vth+deltaVg, the order must be Y, X, X_Value_Lookup, and expressions are supported here for best usability.

Look up or interpolate the derivative of Id with respect to Vgs at your target Vgs

After calculating the first derivative, we present Gm, as shown below.

This Gm data is interpolated at our chosen Vgs, slightly above Vth.

Expand analysis of Gm to observe scaling with respect to device width and length

Next, we can see how these IMV’s scale with respect to device geometry.  In MBP, it’s easy to create plots such as GmNearVth_L and GmNearVth_W, etc.

After saving your work, you may return to the MBP main window to refresh the IMV graphs. We now have transconductance plots ready for model extraction and optimization!

Using a similar approach, we may define other figures of merit to complete the modeling near Vth, for example:

• Ids near Vth
• Gds near Vth
• Rout near Vth

Furthermore, Vth can even be any other IMV or lookup value.

We are excited by the power and flexibility of the Model Builder Program and hope you see the amazing potential that we see daily.  To not only enable the next generation low-power circuit design, but also expand your group’s modeling capability, we look forward to helping you achieve your modeling goals.

Interested in Model Builder Program (MBP) Software? http://www.keysight.com/find/mytrial.mbp.blg

Device Modeling 101 - How to Extract Threshold Voltage of MOSFETs

# Webinar: Managing RF Designs - A presentation by Qorvo Inc and Keysight Technologies

Posted by KeysightEEsofEDA Jan 11, 2017

# Register for Keysight's Latest Tutorial in Signal Integrity Webcast

Posted by KeysightEEsofEDA Jan 5, 2017

Are you a Signal integrity engineer who may not have the time or budget to attend continuing education classes on the latest design tools and techniques? Here's a quick way to invest in your future and update your technical knowledge through these valuable webcasts streamed conveniently to your desktop. This free one-hour webcast introduces a forensic channel analysis approach that implements both measurement hardware and EDA tools with contemporary SERDES internal tools for the purpose of optimizing the BER for highly pathological channels. Register for the Signal Integrity webcast now.

For more information check out Keysight tutorials in Signal Integrity webcast library

# When SPICE Alone No Longer Works

Posted by kaelly_farnham Jan 4, 2017

When SPICE Alone No Longer Works, Channel Simulator Technology May Help

As a designer, chances are you’ve been there. You’re measuring the margin-to-mask for really low bit-error-rates (BER), a task required for high-speed link designs, and the transient simulation (SPICE) you’ve been using no longer seems to work. What are your options? Channel Simulation, as found in Keysight ADS Software, and improved upon in the latest ADS 2016 release, provides a trusted solution.

Before Channel Simulation, the common approach used to simulate a high-speed link design was transient simulation. But, that left designers struggling with questions like: What margin do I have at a BER of 1e-9, 1e-12 or 1e-16?  Transient simulation alone could not deal with these questions because the sheer number of time steps required was beyond practical means.

What margin do I have at a BER of 1e-9, 1e-12 or 1e-16?

The answer to overcoming that hardship lies in being able to compute BER contours with Channel Simulation, a solution built on a strong foundation of technical innovation. Beginning with Dr. Fangyi Rao’s 2006 patent to correct for passivity, while ensuring causality, in bandlimited frequency-domain models, Keysight ADS established itself as the industry-leading Channel Simulator. Using it, you gained access to an accurate solution capable of handling cascades of S-parameter models combined with circuit models in one schematic. In 2009, bit-by-bit channel simulation was released. In 2010, statistical channel simulation was released. In 2011, IBIS-AMI support for channel simulation was introduced. The pace of innovation continues even today, and ADS's channel simulator is widely regarded as the industry standard.

Figure 1. In addition to allowing designers to mix-and-match models, ADS 2016 Channel Simulator now supports IBIS package (.pkg) entries directly, and more extensively than before. It also offers pre-standard support for IBIS v6.1, even before the official IBIS parser is available. Get a free trial of ADS 2016

As the high-speed link designer, you can now freely mix and match models from IBIS, IBIS_AMI and SPICE, as well as generic built-in models (Figure 1). You can even access the Channel Simulator’s own IBIS-AMI Tx and Rx models for PCIe3, USB 3.1 and 100 GbE, which ship with Compliance Test Benches and example workspaces (Figure 2 and 3). Such capabilities are crucial when SPICE alone simply no longer works.

Figure 2. ADS 2016 provides a template for MIPI C-PHY, D-PHY, and in this case, MIPI M-PHY simulation. Get a free trial of ADS 2016.

Figure 3. ADS 2016 features PCIe3 standard-specific EQ presets, which have been added to the PCIe 3 Compliance Test Bench. Get a free trial of ADS 2016.

For more information on measuring margin-to-mask in high-speed link design when SPICE alone no longer works, check out 8 Ways ADS 2016 Helps You Overcome Signal and Power Integrity Challenges.

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