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Threshold voltage (Vth) is one of the most important electrical parameters in MOSFET modeling. There are many existing methods for Vth extraction. Most of these procedures are based on static drain current versus gate voltage characteristics of single transistor. The most popular methods used in industry are

  • Constant Current (CC) method
  • Extrapolation in Linear Region (ELR) method.


The CC method defines Vth as the gate voltage (Vg) required to achieve a chosen drain current (Id) in the device's linear region of operation. Usually drain voltage (Vd) is less than 100mV to bias transistor at linear region and both source and body nodes are connected to ground. Id is determined by (Wm/Lm) x Icon, where Wm and Lm are the mask channel width and length respectively, Icon is the arbitrary value assigned by users. Typical value of Icon is 1e-7. Icon may be different for different process nodes. CC method is widely adopted because of its simplicity. Drawback of CC method is that extracted Vth strongly depends on Icon. The procedure of CC method is shown as Figure 1.

Figure 1: Procedure of Constant Current Method


The ELR method evaluates Vth by finding the intercept at Vg axis of the linear extrapolation of “Id vs. Vg“ curve at the point of maximum trans-conductance (gm). The value of Vth is calculated by subtracting Vd/2 to Vg intercept point to minimize the effect of different value of Vd. The bias condition is the same with the CC method. The procedure of ELR method is shown as Figure 2.

Figure 2: Procedure of Extrapolation in Linear Region Method


In Keysight’s MBP, Model Builder Program, both CC and ELR methods are implemented in built-in libraries and can be easily used in IMV (InterMediate Variable) page as shown in Figure 3.

Figure 3: Vth vs. Length in MBP


For the CC method, MBP also provides different algorithms for you to choose directly:


 Algorithm Class in MBP

 Vth Calculation Method

VTH_CON (x, y, icon)

VTH_CON_LogId (x, y, icon)

VTH_CONW (x, y, icon)

VTH_CONW_LogId (x, y, icon)

VTH_CON_ABS (x, y, icon)

VTH_CON_XWXL (x, y, icon)

VTH_CON_LogId_XWXL (x, y, icon)



[1]  A. Ortiz-Conde et al., “A review of recent MOSFET threshold voltage extraction methods,” Solid-State Electron., vol. 47, no. 4, pp. 677–683, 2003.


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Here’s something that shouldn’t come as a shock to you: data rates are increasing. In fact, multi-gigabit data rates for modern network infrastructure and devices aren’t just an occasional occurrence, they are now the norm. As those data rates increase, you would expect that your electromagnetic (EM) simulation continues to deliver accurate results, but that isn’t always the case. Consequently, picking the right EM technology is now all the more important.


In that regard, you have a few options. Full-wave general purpose EM simulation tools, for example, can be used to achieve the desired accuracy. Faster hybrid simulators, specifically tuned to the requirements of low-GHz applications, can also be used. However, the scale and complexity of today’s PCB designs limits the effectiveness of the 3D-EM simulation; especially when it comes to signal integrity (SI) analysis. If the PCBs are densely routed, it may take hours of engineering time to manually simplify a layout, cookie-cut the signal nets, and optimize the meshing to achieve accurate results. Worse yet, there is always the question of whether or not the simulation correlates well with measurement and if any EM effects were missed?


What’s the solution to these challenges? For those SI engineers looking for an answer, an EM analysis solution specifically targeted at dealing with high-speed links on large, complex high-speed PCBs is a good place to start.

 SIPro, ADS 2016, signal integrity

Figure 1. With ADS’s SIPro, signal analysis can be completed in just a fraction of the time it would take using a more traditional approach.


SI EM analysis, available in ADS 2016 SIPro solution, utilizes composite EM technology to deliver pure-EM analysis. By doing so, it captures all relevant EM effects, such as via-via coupling and via to microstrip transitions. A net-driven interface allows you to select only those nets you want to simulate, along with the relevant power and ground planes, as well as components. With no engineering effort or time needed on your part to manually edit or manipulate layout objects, you can quickly perform EM simulation. You can even automatically set up ports. It’s a workflow that can take you from layout to results in under 20 clicks (Figure 1).

SIPro, ADS 2016, signal integrity         

Figure 2. SIPro delivers results approaching the accuracy of full-wave 3D-EM solutions, but in a fraction of the time.


Once EM simulation is finished, you can plot the S-parameters, TDR/TDT and crosstalk to quickly determine if your EM model is sufficiently characterized and if your channel is performing as expected (Figure 2). Furthermore, with a single-click, automatic schematic generation back-annotates the EM model, making it ready for you to use in both transient and channel simulations.


For more information on overcoming this and other signal integrity or power integrity challenges, check out 8 Ways ADS 2016 Helps You Overcome Signal and Power Integrity Challenges.


You can now download Andy Howard, Senior Application Engineer at Keysight, updated example that shows different techniques for simulating the X-dB gain compression point of an amplifier or device (and that includes load pull.) The updated version now includes calculations of the X-dB gain compression using the small-signal gain as the reference, the maximum gain as the reference, and the gain at a user-specified available source power as the reference. You may download the example from the Keysight EEsof Knowledge Center (a login is required):