This year DDR4 shipments are expected to reach 35% of total dynamic random access memory (DRAM) shipments, an increase of 15% from last year (source: IC Insights).
The top speeds of these DRAM devices bring forth a legion of signal integrity and power integrity concerns that if the designer doesn't approach systematically, will leave margin, performance and reliability on the table. At the present, top speeds for DDR4 (without overclocking) are 3200MT/s, and an interesting point to note is that this top rate is expected to double when the next generation technology comes through (the DDR5 spec is currently being worked on in JEDEC).
Minimizing reflections, crosstalk, and selecting the optimum termination choices , and will become paramount in the near future.
Reaching confidence in a DDR4 design requires setting up an Electromagnetic (EM) simulation of the PCB layout.
A key step to reaching confidence in a design is setting up an Electromagnetic (EM) simulation of the PCB layout, to catch issues before fabricating the board. This requires high-frequency accuracy of an EM solver in a productive workflow. This is especially important for DDR, where the number of IOs are exceptionally high. Setting up ports and sifting through data has been onerous in EM simulation solutions in the past.
Starting a design in DDR4? 8 steps to ensure success
- Begin with a DDR bus simulation in schematic, typically for a single byte lane of data (DQ) lines with data strobe, and a similar setup for the full-rate command/address lines, using your desired substrate stackup. The starting point is usually a reference design from the CPU/Memory Controller vendor, but of course you are not constrained to this. The bus simulation will allow you to easily sweep multiple parameters at once (for instance: On Die Termination values for the DRAM IOs), such that you identify the physical layout constraints for the link, or optimize the interconnects for higher performance and/or more margin. DDR bus simulation allows you to quickly see what the dominant factors are, by enabling/disabling crosstalk aggressors, and looking at the eye diagram at any point in the chain.
Pre-layout exploration is important to look for things such as inter-symbol interference in the channel, random and deterministic jitter, and degredation due to VCC bounce.
- Swap to a Transient simulation on the same schematic, and check that the time-domain measurements like skew, overshoot, undershoot, and timing have enough margin to the specification.
- Create the PCB layout once an optimized design has been reached. The finished (or partially-finished layout) can be imported to a design tool for an EM simulation (for example, to ADS for simulation with SIPro).
A critical step to a successful DDR4 design is performing and EM simulation to catch issues before fabrication.
- Perform an EM simulation to capture any of the unforeseen issues that were not present in the schematic. Issues like voids in the ground plane, or crosstalk in the via pin fields being worse than expected.
- Inspect the resulting S-parameter data for the PCB for quality and any obvious issues that may have been found in the layout. E.g. transmission on one line sees more loss than the others, or has a resonance when the others do not. With near-end and far-end crosstalk responses plotted, are there any that stand out as being much higher crosstalk levels than the rest? Note: If the power distribution network design is ready, this can be easily added to the same EM simulation as well.
- Replace the physical interconnect models with the new EM model in the schematic from step 1. Run a DDR bus simulation to verify the margin to the Receive BER mask is still acceptable. A BER of 1e-18 is required for command/address lines, which is why the statistical bus simulation is so important.
- Run a transient simulation of the same schematic, whereby the power supplied to the Tx and Rx components (represented as power-aware IBIS models) can be realistic, traveling through the EM model of the PDN before arriving at the IC. In this way, Vcc sag & Ground bounce are modeled, and the eye diagram will be noisier. Measuring the added jitter and peak-peak amplitude noise, means that this information can be used to adjust the Rx BER mask as used in step 6.
- Analyze the worst-case traces with a DDR4 compliance test bench to cement confident in your design procedure. A compliance test bench uses the same compliance test software on the simulated waveforms as is used on the test bench with your first prototype system, now fabricated and ready to probe.
Before committing the board to prototype, the waveforms can be used with software to perform a DDR4 Compliance Test.
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