How to Reduce Respins by Using FPGA Prototyping Inside a Complete Flow

Blog Post created by AlyssaRao Employee on Jul 7, 2016

Field Programmable Gate Array (FPGA) prototyping is already known to be a standard technique to verify the functionality and performance of ASICs, ASSPs, and SoCs. It is increasing in popularity today due to increasingly complex systems, especially in FPGA-based communications and radar systems.

We already know the benefits of FPGA prototyping: higher performance, portability, and availability (because of relatively lower cost). Using FPGA prototyping inside a complete design flow has even more benefits and enables FPGA-based communications and radar systems to be designed, verified and implemented even faster. FPGA application developers can more quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurement, such as bit-error-rate (BER).Let’s look at an example of how a design flow can reduce respins in FPGA prototyping.

Our example is a military communication receiver inside a model-based design approach to a software-defined radio (SDR) flow that moves from system-level architecture to hardware verification.


The above conceptual diagram breaks the FPGA prototyping design flow into 8 steps. It shows a design flow with SystemVue and a model-based verification flow. The process uses standard SystemVue libraries in both floating and fixed point for design and verification, along with FPGA implementation tools from Xilinx and Aldec. In this design flow the testing, I/O functions and some timing synchronization algorithms are also included.

SDR FPGA Design to Verification Flow in 8 Steps:

  1. System design & validation in floating point
  2. System design & validation in fixed point
  3. HDL code generation
  4. HDL validation using co-simulation with Aldec Riviera-PRO
  5. Generation of the FPGA programming file
  6. Loading of the.bit file into the FPGA
  7. Generation of test signals for FPGA receiver test
  8. Testing of the FPGA


The details of these 8 steps are outlined in the application note, FPGA Prototyping Using Keysight SystemVue, but we will highlight a few key points in this blog post. The app note walks through all 8 steps, showing screenshots of the Keysight SystemVue Electronic System Level (ESL) design software throughout. Keysight SystemVue provides an easy graphic programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation.

Using these 8 steps designers can reduce respins in FPGA prototyping.

The first step in this flow is the design process to create a working model that can be used to validate the receiver algorithms, first under ideal conditions, and then under a variety of stressful conditions (e.g., impairments and noise). This initial architectural and algorithmic modeling can be done using floating-point models in any of several formats: built-in graphical blocks, C++ or math language (.m).

The floating-point design for the Frequency Shift-Keying (FSK) system, including transmitter, communications channel and receiver is below.


Connecting to test improves the fidelity of system architecture design. Conversely, leveraging the design platform for early R&D validation creates new value for test. Simulation is used to validate the overall FSK system. Using internal SystemVue graphs or external 89600 VSA software, the transmitter output is first verified to ensure the time waveform and frequency spectrum are acceptable.

The next step on the path to a hardware implementation is to consider the effects of quantization and finite-precision arithmetic on the algorithms. Will they still work? How much precision is required for the specified system performance?

In our example, SystemVue’s fixed-point library is used to consider these questions. The W1717 Hardware Design Kit is a SystemVue design personality that not only includes the fixed-point library and its diagnostic simulation support, but also VHDL/Verilog code-generation. Below is the fixed-point design for the FSK receiver.


The next steps in this example are hardware implementation of the baseband receiver and BER tester. In the final step the FPGA performance is tested. First, we verify the input FSK signal by connecting a signal generator’s RF output to a RF signal analyzer, and we observe the FSK signal.


With this setup, we see the test and reference bits are aligned, and the expected numbers of errors are observed. Success! To see all the steps in more detail, I recommend reading the application note, FPGA Prototyping Using Keysight SystemVue.

Imagine how much faster FPGA-based validation would be with a system-level simulation tool integrated into the hardware design flow, for leading edge wireless and radar systems. Keysight SystemVue provides an easy graphic programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation. Although hand-coded VHDL can be quite powerful, from a project perspective it is more efficient to use HDL code-generation from the system level in a model-based design flow, reducing development and verification time.

Although we referenced specific applications and hardware platforms, the design flow for FPGA prototyping can apply to a variety of platforms and vendors. By going through this example we can see how a FPGA prototyping design flow helps simplify the design of complex systems, reducing respins, and helping to cut costs.

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