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Note: A more polished version of this Case Study is available in PDF format as STMicroelectronics & ESEO Use ADS To Design a 2.45 GHz Wireless Power Scavenging Circuit. There is also slightly different version: Extending the Operating Life of IoT Devices with a Wireless Energy-Harvesting Circuit.


Previously I posted a Case Study about a wireless power scavenging circuit whose impedance matching circuit was built around a high Q quartz crystal resonator. This particular component works best at 24 MHz. One of the comments I received on the LinkedIn syndication of that posting asked about similar circuits, but in the microwave regime. This band is important because there is more ambient RF energy floating around at 1.8 GHz (e.g. GSM1800 from cell towers) and 2.45 GHz (from WiFi) than at 24 MHz. So I searched around and the result is this new Case Study about series of papers by Dhaou Bouchouicha and Mohamed Latrach et al. They are at ST Microelectronics and Ecole Supérieure d'Electronique de l'Ouest (ESEO) in France. The papers include An Experimental Evaluation of Surrounding RF Energy Harvesting Devices and Hybrid Rectenna and Monolithic Integrated Zero-Bias Microwave Rectifier.

The Challenge

To rectify the ambient RF/microwave energy, the matching circuit must put a voltage across the rectifying diode that exceeds the forward voltage drop, typically 0.3V for Schottky diode. The antenna gathers less than a microwatt of power, so we need a big impedance transformation from the antenna impedance (something on the order of the impedance of free space, 377 ohms) to several kiloohms.

The Solution

The authors used ADS co-simulation of the Momentum EM field solver and Harmonic Balance circuit solver to optimize the rectenna (rectifier + antenna) design. They included diode package parasitic models, which enable them to get good correlation between simulation and measurement. By carefully tuning the distance "d" between the matching capacitor and the SMA connector (shown in their figure 3 reproduced below) they optimized the convection efficiency. 


The Results

With a patch antenna with dimensions of about 20 mm on a side, they obtained a DC power of 1.3 microwatts with an input power of 10 microwatts, yielding an efficiency of 13%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

Work your way through the examples to design an amplifier and an active mixer. Learn how to tune and optimize your design. Become familiar with ADS libraries and quickly add components to your design. Great for beginners, the step-by-step screenshots demonstrate how to get started using ADS without assuming any prior experience. Download the ADS Example book now.



Keysight Technologies, Inc. (NYSE: KEYS) today announced the newest release of its high-performance, Advanced Low-Frequency Noise Analyzer (A-LFNA), which is designed to make fast, accurate and repeatable low-frequency noise measurements. The release features a new user interface and tight integration with Keysight's WaferPro Express software — a platform that performs automated wafer-level measurements of semiconductor devices.

More information about the A-LFNA is available at Images of the analyzer are available at A video on A-LFNA is available on YouTube at

(Note: A more polished version of this posted has now been published as a PDF entitled NCK University Uses ADS to Create an Impedance Matching Method for Wireless Battery Charging)


In a previous Case Study I pointed out work that used a high Q quartz crystal resonator for wireless power transfer at 24 MHz. The load in that case was a switched-mode power converter. But what if you want to charge a battery directly? It's tricky because the resistance, reactance, and the cell voltage of a rechargeable battery all vary dramatically with its state-of-charge. What load do you optimize the matching network for when the load is dynamic? In their paper Direct current driving impedance matching method for rectenna using medical implant communication service band for wireless battery charging, H-W Cheng, Tsung-Chi Yu, and Ching-Hsing Luo of National Cheng Kung University address this problem with a simple yet effective method using Advanced Design System. They also used ADS EM-circuit co-simulation to design the printed circuit antenna.

The Challenge

Within a tiny 14 mm (0.55 inch) diameter disk, the wireless battery charger has to include a printed circuit antenna, matching network, two rectifier diodes, and an LC low pass filter. The received RF power was a mere 10 mW at 405 MHz. The challenge is to recharge the Li-ion cell, which had a 10mA.hour capacity, in 5 hours (a so-called "0.2 C rate"). The charging current was 2 mA but the cell voltage varies from 3.0V (empty) to 4.2V (full) and impedance varies wildly with state-of-charge.

The Solution

The authors employed ADS harmonic balance to simulate the circuit and explore the design space. Using a sweeping method detailed in the referenced paper, they came up with a optimized circuit consisting of only three capacitors, one inductor, two diodes, and of course the PCB itself, which includes not only interconnect but also the antenna, designed using ADS EM-circuit co-simulation.

The Results

Figure 7 of their paper shows the finished implementation. They achieved 76% conversion efficiency of incident power to battery charging power averaged over a five hour charge cycle. Comparable prior work achieve only 50%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

Why do I love my job? It’s the brilliant people I get to work with every day, like Bob Witte. He is now the Vice President of Technology Strategy at Keysight Technologies and he wrote a textbook in his spare time!

At IMS in May 2016, Bob Witte signed copies of his 2nd edition of his popular “Spectrum and Network Measurements” book on the show floor. Watch this 4-minute video to hear from the author himself. His passion for helping new engineers is evident. He says, "This is the book I wished I had when I started working because it pulls together the basics in an industry-focused way."


His book is an introduction to spectrum analyzer measurements and network analysis and it covers Fourier analysis, transmission lines, intermodulation distortion, signal-to-noise ratio and S-parameters. Get a copy and give it to a new engineer you know as a gift (available on Amazon).


I love getting to work with experts like Bob Witte every day! That’s Keysight Technologies!


Note: A more polished version of this Case Study is available in PDF format as STMicroelectronics and University of Lyon Predict EMI Using ADS.


This Case Study highlights work in a paper N-Conductor Passive Circuit Modeling for Power Converter Current Prediction and EMI Aspect by Roberto Mrad, Florent Morel, Cael Pillonnet, Christian Vollaire, Phillppe Lombard, and Angelo Nagari. The high di/dt edges in switched-mode power supplies (SMPSs) can create EMI problems especially if the layout has long power and ground traces. To explore the design space, you need a good model of the impairment you are trying to mitigate. Prior modeling work used lumped elements, but these are not great a modeling traces, which are transmission lines. You'd need an infinite number of infinitesimal LC ladder segments to model a trace exactly. Mrad took a leaf out of the RF/microwave playbook and used network parameters instead.

The Challenge

Conducted electromagnetic emissions from switched-mode power supplies (SMPSs) interferes with the adjacent circuits they are powering. To avoid failure, EMI filtering is added. To design cost effective EMI filtering, it is necessary to explore the design space efficiently. Cut-and-try is too time consuming and so simulation is preferred. But to do simulation, you need accurate models and conventional lumped element models of the traces are not adequate.

The Solution

Traces and vias are essentially delay lines (exp(s) in Laplace space) whereas lumped element L's and C's are integrators/differentiators (s or 1/s in Laplace space). For this reason, lumped element ladders are not efficient at modeling traces. Fortunately network parameter models are readily available and work efficiently in both frequency and time domain simulation. They work directly in AC or harmonic balance (HB) frequency domain circuit analysis or via convolution in the time domain. (Convolution is a way of building a time domain delay line model from frequency domain data using a "smart" inverse fast Fourier transform (IFFT).) The authors used Advanced Design System because it handles network parameters both from measurement instruments and from transmission line models.

The Results


The authors obtain excellent correlation with measurement as you can see in Figure 18 of their paper:


They went on to use the model to design a compact and low cost EMI filter using a sophisticated optimization algorithm, also using ADS. That paper is called Discrete Optimization of EMI Filter Using a Genetic Algorithm but we'll save that Case Study for another day.



Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

This video shows how circuit simulation, integrated with 3D EM simulation, is used to optimize the performance of a low-pass filter design. An example of coil inductors on a PCB illustrates how integrated 3D EM simulation is used to move from an ideal filter design to a physical design. 3D coil inductor models are created in Keysight's EMPro software and used in Keysight's ADS software, where a full 3D EM simulation analyzes all of the physical effects, including parasitics of the filter.

For a free evaluation copy of EMPro:

In this application note, you will learn the following topics:


– Basics of noise spectral density
– Noise measurement applications
– Practical considerations in noise measurements
– How the E4727A addresses noise test challenges


Download A-LFNA app note.

Watch this live demo and see the latest for phased-array beamforming software for 5G, Radar, and EW Systems.



Introducing SystemVue 2016

See a live demo of SystemVue 2016. The new capabilities enable researchers and system architects working on platforms using beamforming algorithms for 5G, satellite, NewSpace, radar and EW applications, to reduce interference and power...


New video from Franz Sischka shows how to verify s-parameters for obtaining reliable device models. After a quick recap of the network analyzer basics, this video presents a step-by-step guide to master S-parameter measurements, and to get accurate and verified data right the first time.



Download his IC-CAP project here and get started on your own design:


Topics covered:
- measurement of the DC bias contact resistance
- evaluation of the right RF signal power to not overdrive the transistor
- S-parameter calibration and verification
- verification of the de-embedding dummy structures
- identification of self-heating problems during S-parameter measurements
- examples of accurate S-parameter measurements

Being new to power electronics, I've been going back through the literature to find out how engineers use Advanced Design System for their switched-mode power supplies (SMPSs) and wireless power transfer (WPT) systems. I'm going highlight a selection of these in this series of postings I call Case Studies. The first is a paper from 2009 on WPT. I initially posted this on my LinkedIn blog but with the launch of this new blog, I'm migrating over to this new site. A more polished version is available as a PDF "Ericsson and Freiburg U. Design High Q Power Harvesting Circuit Using ADS."

This Case Study is about a paper titled RF Energy Harvesting Design Using High Q Resonators by Xavier Le Polozec of Ericsson and Tolgay Ungan, William Walker, and Leonhard Reindl of the University of Freiburg. Their goal was wireless power of a couple of hundred nanowatts at 1V to power a sensor node. The transmitted power was at 24 MHz. They used ADS harmonic balance to explore the design space particularly around the innovative impedance transformation using a high Q quartz crystal resonator to transform the low voltage from the low impedance antenna to a voltage high enough to overcome the Schottky diode junction voltage (about 0.3V).


The Challenge

The tricky part here is that government regulations generally limit the transmitted power such that the harvesting antenna only receives at most -30 dBm (1 μW). Prior solutions had only ~10% total efficiency. To power their sensor they needed a conversion efficiency > 20%. They added a high Q quartz crystal resonator to introduce an impedance transformation between the antenna and the rectifier. The antenna impedance was 50 ohms so voltage with 1 μW is only about 7 mV, not enough to forward bias the Schottky microwave detector diodes (Avago HSMS-2862). The transformer boosts the voltage so that diodes, used as rectifiers in a half bridge configuration, are forward biased and conducting on their respective positive half cycles. The challenge was to satisfy the impedance matching requirement when the antenna, resonator, and matching components were loaded with the nonlinear diodes.


The Solution

The authors used the ADS Harmonic Balance simulator to help design the impedance matching circuit. Unlike SPICE simulators, which typically only handle linear circuits in the frequency domain ("AC analysis"), ADS Harmonic Balance handles nonlinear effects and gives you the periodic steady state solution without having to wait for the startup transient to die down. In contrast ordinary time domain ("transient analysis") requires this time consuming step. They could quickly explore the design space with a set of trustworthy simulations before committing to fabrication. Once the design was optimized, they invested in building the prototype.


ADS harmonic balance gives us trustworthy simulations before committing to fabrication. We can estimate the influence of each parameter over the global circuit response, tuning and optimizing the circuit before committing to fabrication. We get good correlation with subsequent measurements on hardware.

-- Xavier Le Polozec, Senior Technical Subject Matter Expert, Ericsson


The Results

They achieved excellent correlation with measurement and the circuit delivered the required efficiency. The simulation correctly predicted that the peaks of the family of curves of efficiency versus frequency would shift. The nonlinearity of the diodes cause the peak to shift about 200 Hz as the input power is increased from -50 dBm to -20 dBm. This subtle effect was seen in both simulation and measurement.


An input of only 7 mV rms at 24 MHz (1 μW into the 50 ohm antenna) yielded an output of 1 V DC and a measured overall efficiency of 22.6%.


Are you working on wireless power transfer? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

Best regards,

-- Colin

PS Here's the link to request an ADS evaluation license if you want to try it.

This video shows how to model nonlinear magnetic components as part of a complete switching convertor circuit simulation. Switched-mode power supplies use inductors with a ferromagnetic core, and these nonlinear materials exhibit saturation and hysteresis in their magnetization curve. Learn how to implement the physics-based Jiles-Atherton model, and couple electric and magnetic circuits with Faraday’s and Ampere’s laws to to create a complete switching converter circuit simulation.


To download the project files referred to in this video visit:


After a brief introduction to challenges such as size, weight, efficiency, cost, and robustness in power module design for power electronics, this webcast will lay out a new workflow for such projects that include modeling and characterization of components and devices such as GaN transistors, electro-thermal co-simulation, and integration of GaN into power electronic circuits. We conclude that EDA tools originally intended for RF/microwave design have much to offer in such a workflow.


Accompanying Slides:


You design tomorrow’s technology. Keysight’s “How to” series connects you with the expertise of our top engineers.

Watch veteran RF Design Engineer Matt Ozalas as he shares his unique design methodology to provide you the building blocks for more complex PA classes.

Download Matt’s easy-to-use PA workspaces to save time by starting out with a solid circuit topology.

Click the link in the video below to view the series.

We were asked a very interesting question on our YouTube channel regarding our video, How to Design an RF Power Amplifier: The Basics.

"Hey Matt, that was an awesome tutorial. However, I'd like to have your opinion on the impact of S22 on the performance of an RF Power Amplifier. And how it might affect the various Figures of Merit. Thanks. :)"

Since it's quite a long discussion, so we've posted the answer here.

It can be confusing. The load line match needed for the optimal PA operation is not at all the conjugate match scenario which is described in standard microwave engineering courses where one tries to present S22 conjugate back to the transistor through an output matching network. You may recall that a conjugate match is set up to obtain maximum power transfer between two small signal blocks. If you think about it, the assumption that there is that the power available from the generator is constant, and in that case the conjugate match results in maximum output power (and by extension maximum power gain) because as much power as could be transferred to the load was transferred to the load. The difference is that power from the generator in the large signal (PA) case is not constant at all. In fact for large signal cases, the power generated depends heavily on the load presented to the device because this load effectively limits the possible excursions of the voltage and current waveforms.

In the classical theory, there is only a load line match; a conjugate match is not relevant. Practically, maximum power generation described by the load line approximation only occurs for one single condition of bias and input drive.

For the classical modes the power predicted using the loadline approximation is the output power achieved somewhere around the 1 dB gain compression point, give or take a few tenths of dBs. However, most communication systems have complex modulation formats whereby the input signal is not fixed power at all; instead, the useful information is modulated onto the drive signal, resulting in variation in both amplitude and phase. The power amplifier is likely to see some drive signals which are low power and others which are high power all contained within the same modulated envelope. Some of these signals will have drive levels that will not push the PA very hard, others will push the PA to its limits (maybe even past the gain compression point). To a first order, the transition of the gain (and phase) characteristic from the small signal to large signal regions is what determines the level of spectral regrowth in the frequency domain. High levels of spectral regrowth can interfere with nearby adjacent channels. So then perhaps there is some need to consider PA performance for small signal drive levels after all …[sigh].

It turns out that there can actually be many different loads presented to the device which can all result in basically the same power and efficiency in a large signal sense. For an example of this, check out this video on continuous modes of operation.

If there are in fact multiple large signal loads that are all pretty much the same performance wise, what’s the best one to choose?

To make a long story short, it may be possible to pick a load (and bias level) which both delivers the desired large signal output power plus efficiency at compression while at the same time providing a small signal match which results in a favorable backed off power gain characteristic. In that way, the transition between the small signal region and large signal compressed region can be managed so that it is not overly expansive or compressive but occurs in a smooth, idealistic manner with only minimal compression at the maximum output power required, thereby giving minimal spectral regrowth.

All else being equal, that type of amplifier which has a good mix of large signal and small signal performance will perform best when put into a real life communication system. It’s likely that the load chosen is neither a perfect load line match nor a perfect conjugate match, but a tradeoff between the two.

Field Programmable Gate Array (FPGA) prototyping is already known to be a standard technique to verify the functionality and performance of ASICs, ASSPs, and SoCs. It is increasing in popularity today due to increasingly complex systems, especially in FPGA-based communications and radar systems.

We already know the benefits of FPGA prototyping: higher performance, portability, and availability (because of relatively lower cost). Using FPGA prototyping inside a complete design flow has even more benefits and enables FPGA-based communications and radar systems to be designed, verified and implemented even faster. FPGA application developers can more quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurement, such as bit-error-rate (BER).Let’s look at an example of how a design flow can reduce respins in FPGA prototyping.

Our example is a military communication receiver inside a model-based design approach to a software-defined radio (SDR) flow that moves from system-level architecture to hardware verification.


The above conceptual diagram breaks the FPGA prototyping design flow into 8 steps. It shows a design flow with SystemVue and a model-based verification flow. The process uses standard SystemVue libraries in both floating and fixed point for design and verification, along with FPGA implementation tools from Xilinx and Aldec. In this design flow the testing, I/O functions and some timing synchronization algorithms are also included.

SDR FPGA Design to Verification Flow in 8 Steps:

  1. System design & validation in floating point
  2. System design & validation in fixed point
  3. HDL code generation
  4. HDL validation using co-simulation with Aldec Riviera-PRO
  5. Generation of the FPGA programming file
  6. Loading of the.bit file into the FPGA
  7. Generation of test signals for FPGA receiver test
  8. Testing of the FPGA


The details of these 8 steps are outlined in the application note, FPGA Prototyping Using Keysight SystemVue, but we will highlight a few key points in this blog post. The app note walks through all 8 steps, showing screenshots of the Keysight SystemVue Electronic System Level (ESL) design software throughout. Keysight SystemVue provides an easy graphic programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation.

Using these 8 steps designers can reduce respins in FPGA prototyping.

The first step in this flow is the design process to create a working model that can be used to validate the receiver algorithms, first under ideal conditions, and then under a variety of stressful conditions (e.g., impairments and noise). This initial architectural and algorithmic modeling can be done using floating-point models in any of several formats: built-in graphical blocks, C++ or math language (.m).

The floating-point design for the Frequency Shift-Keying (FSK) system, including transmitter, communications channel and receiver is below.


Connecting to test improves the fidelity of system architecture design. Conversely, leveraging the design platform for early R&D validation creates new value for test. Simulation is used to validate the overall FSK system. Using internal SystemVue graphs or external 89600 VSA software, the transmitter output is first verified to ensure the time waveform and frequency spectrum are acceptable.

The next step on the path to a hardware implementation is to consider the effects of quantization and finite-precision arithmetic on the algorithms. Will they still work? How much precision is required for the specified system performance?

In our example, SystemVue’s fixed-point library is used to consider these questions. The W1717 Hardware Design Kit is a SystemVue design personality that not only includes the fixed-point library and its diagnostic simulation support, but also VHDL/Verilog code-generation. Below is the fixed-point design for the FSK receiver.


The next steps in this example are hardware implementation of the baseband receiver and BER tester. In the final step the FPGA performance is tested. First, we verify the input FSK signal by connecting a signal generator’s RF output to a RF signal analyzer, and we observe the FSK signal.


With this setup, we see the test and reference bits are aligned, and the expected numbers of errors are observed. Success! To see all the steps in more detail, I recommend reading the application note, FPGA Prototyping Using Keysight SystemVue.

Imagine how much faster FPGA-based validation would be with a system-level simulation tool integrated into the hardware design flow, for leading edge wireless and radar systems. Keysight SystemVue provides an easy graphic programming environment to simulate and verify system performance prior to realizing a dedicated hardware implementation. Although hand-coded VHDL can be quite powerful, from a project perspective it is more efficient to use HDL code-generation from the system level in a model-based design flow, reducing development and verification time.

Although we referenced specific applications and hardware platforms, the design flow for FPGA prototyping can apply to a variety of platforms and vendors. By going through this example we can see how a FPGA prototyping design flow helps simplify the design of complex systems, reducing respins, and helping to cut costs.

For more information about this specific application with SystemVue, please visit the following:

Check out more application examples in the ESL Application Center!

Apply for a FREE trial of SystemVue now!

If you missed our webcast on February 5, be glad. You would have been standing. Okay, just kidding, it was an online webcast, but we had a record number of people on the line clamoring for their question to be answered during the Q&A session. You missed out.


The good news is that the recorded version and slides are now available here. So grab a cup of coffee, take a seat, and learn about what is currently being done in 5G research at the physical layer.


For those who just want the highlights, keep reading. In this post and the next two, I’m going to cover the highlights from that webcast.



If you missed it live, click the picture to watch the on-demand version.

Researching Waveform Techniques for 5G

Today I’d like to highlight the most interesting part (I believe) of 5G research today, waveform techniques.  The webcast covered 3 waveforms:

  1. Orthogonal Frequency Division Multiplexing (OFDM)
  2. Filter Bank Multicarrier (FBMC)/Generalized Frequency Division Multiplexing (GFDM)
  3. Universal Filtered Multicarrier (UFMC)


Designers are currently investigating which waveform would meet all of the requirements that 5G would demand. This includes such considerations as: efficiently supporting high density users, optimizing multiple accesses, efficient use of spectrum, robustness to narrow-band jammers and impulses, and many others. The webcast covered the advantages and disadvantages of each waveform for 5G.

ESL_Figure 1.jpg

OFDM vs FDMC spectrum using different filter overlap factor (photo credit: Understanding 5G webcast)


It was a very interesting discussion, and, spoiler alert, it looks like OFDM is currently leading the way, but I encourage each of you to listen to the webinar for yourself.

ESL_Figure 2.jpg

GFDM vs OFDM (photo credit: Understanding 5G webcast)

The discussion concluded with an end to end performance simulation of an FBMC reference source and receiver. It was a great way to visualize and sum all signal processing techniques in one model. It made a lot of sense for any type of physical layer designer who is researching new communications systems.

ESL_Figure 3.jpg


What happened to the RF?

Posted by AlyssaRao Employee Jul 7, 2016

This is the second of three posts covering the highlights from the recent webcast, Understanding 5G and How to Navigate Multiple Physical Layer Proposals. In the first post, we talked about the different waveform techniques currently being investigated for 5G. Today I’m going to share a case study of a possible 5G modeling and simulation example at 28 GHz frequency band and 500 MHz bandwidth.

Physical layer designers know that their goal is to consolidate the hardware requirements of a network to enable the successful transmission of data. In order to do that, they need to consider both baseband and RF modeling together. In this example we will consider a 28 GHz frequency band and 500 MHz bandwidth. You can see the setup in the block diagram below.


Block diagram of a 28 GHz frequency band and 500 MHz bandwidth. (Photo credit: Sang-Kyo Shin’s Understanding 5G webcast)

We chose a Filter Band Multicarrer (FBMC) Source for modeling the baseband in the time domain. For 5G opportunities, FBMC is being considered by many as a viable alternative to Orthogonal Frequency Division Multiplexing (OFDM).  FBMC tends to have lower Adjacent Channel Leakage Ratio (ACLR) than OFDM. In this model we combined the Baseband and RF blocks. Both the baseband and RF designers will need to work together for this simulation to be successful. Let's consider the spectrum outputs of each.


FBMC Baseband Spectrum and RF spectrum. (Photo credit: Sang-Kyo Shin’s Understanding 5G webcast)

We already know FBMC already has good performance, and when we consider the FBMC Baseband Spectrum output it looks pretty good. But what happened to the RF?

When we consider the RF spectrum we see out of band leakage. What can we do to meet the spectral requirement of the transmitter signal? Experienced physical layer designers probably know the answer. We need to address the Peak-to-Average Power Ratio (PAPR) problem. This is a common problem for both OFDM and FBMC.  There are many PAPR reduction methodologies being researched in signal processing for 5G today. One of the latest techniques currently being investigated is clipping.  These researchers are using models and simulation such as this one to compare performance. Find out more by watching this webcast.

This post covers the new video on YouTube, How to Understand 5G: Beamforming. In this “How To” video you will learn about some fundamental concepts, functionality, and design applications of three types of multi antenna beamforming architectures at the system level. You will also learn about beamforming techniques being proposed for 5G and how they affect mobile communication performance. As antenna arrays get more sophisticated and increase in operating frequency the use of accurate system modeling and the channel effects are becoming crucial in the design process.

Baseband Beamforming architectures


Figure 1. Baseband Beamforming System Architecture: Weighting factor Wi is a function of amplitude and phase with i {1..n} as number of antenna paths, precoding and combining are performed in BB.

In the baseband beamforming architecture we get large antenna gain and this enables multi stream, multi user connections with a variety of transmission modes. However, one of the biggest challenges designers face is when the design requires hundreds of antennas, which all need hundreds of power-hungry converters (both analog to digital and digital to analog). This high power requirement will increase hardware complexity and power consumption of the system and makes this architecture impractical for these types of designs. As a result, digital beamforming architecture is mainly used in mobile applications in base station downlink transmitters. It is interesting to note that because of digital beamforming’s high power consumption some of the digital beamforming proposals are for receivers to mitigate uplink inter cell interference.

RF Beamforming architectures


Figure 2. RF Beamforming Receiver Architecture: Weighting factor Wi is a function of amplitude and phase with i {1..n} as number of antenna paths, precoding and combining are performed in RF.


In RF beamforming all the precoding and combining is done in the RF side. Compared to digital beamforming there are implementation advantages in terms of lower power consumption and lower hardware complexity.

Since high performance phase shifters in CMOS introduce phase and amplitude error verses frequency as well as phase variation verses the control voltage, the design of high performance phase shifters in CMOS turns out to be quite challenging. Some of the early 5G prototyping systems in the 63.5 GHZ frequency band has been proposed using RF beamforming architecture.

Hybrid Beamforming architectures


Figure 3. Hybrid Beamforming System Architecture(Shared Array):
Baseband precoder(FBB) / combiner(WBB) using digital signal processing and RF precoder (FRF) / combiner(WRF) using phase shifter.


The hybrid beamforming structure combines the strengths of both analog and digital beamforming systems to reduce overall hardware complexity. In the hybrid structure the precoding and combining is done in both baseband (BB) and RF sections. By reducing the total number of the RF chains and analog to digital and digital to analog converters, hybrid beamforming still gets similar performance to that of digital beamforming, but saves power and complexity. With this structure even though we used a large enough number of antennas, the lossy mmWave channel naturally suppresses multi path interference and reflections.

You can design a real world multi antenna system using Keysight’s 5G simulation library and multi-channel RF models by following this “How To” video.

When designing mixed signal components you have to consider issues such as high sampling rates, quantization error, jitter, and high power consumption. In the antenna arrays at the system level you need a new mmWave channel model that supports multiple antenna paths and bandwidth in order to get a realistic picture of system performance. All of these complex issues can be solved only when you utilize trusted reference algorithmic modeling and innovative simulation methodology. Keysight SystemVue makes it easy to investigate new system architectures and create reliable system proposals and specifications. Also 3D visualization can help you identify and address problem areas that improve system performance at an early stage of your design.

Watch “How to understand 5G beamforming“ and download the workspace at: now to get a head start with your 5G communication design.

Virtual Flight Testing of Radar System Performance

Flight testing is the primary method for evaluating the performance of a radar system. While an aircraft is in flight, data such as probability of detection, signal strength, and clutter might be gathered. Though effective, this approach does pose a number of testing challenges. The following explores the use of virtual flight simulation in the interest of saving time and money, while also increasing accuracy.

Challenges of Flight Testing:

  • In order to obtain statistically significant results, a large number of flights must be performed in order to yield an adequate data sample. The costs incurred in hands-on flight testing are thus sizeable. This method is simply too cost-prohibitive.
  • The data and test conditions from one flight run to the next are not repeatable, resulting in the need for multiple runs, and thus more money. Without the ability to easily replicate results, the time involved in the test environment is increased.

A Potential Solution:While in-field operational verification may still be necessary for contractual or legal reasons, “virtual flight testing” is a faster, more cost-effective alternative for earlier stages of R&D. The ability to simulate the full deployment and flight environment enables exceptional development speed and provides rapid prototyping capabilities of any radar system environment. With lessened time and money involved, simulation poses a viable solution to the testing challenge.In simulation:

  • Complex radar systems can be evaluated hundreds of times in an hour (Using the same/different scenarios for each run).
  • By evaluating realistic flight-testing scenarios before or in place of physical flight testing, engineers can validate electronic warfare algorithms earlier, saving both time and money.

The Virtual flight test solution was created by combining the capabilities of  Keysight SystemVue software with those of the AGI STK tool from Analytical Graphics. The W1461BP SystemVue Comms Architect is electronic system-level design software that integrates modeling, simulation, reference IP, hardware generation, and measurement links into a single, versatile platform. It enables system architects and algorithm developers to innovate the physical layer (PHY) of wireless and aerospace/ defense radar and communications systems, and provides unique value to RF, DSP, and FPGA/ASIC implementers. The W1905 Radar model library provides baseband signal processing reference models for a variety of radar architectures.


Figure 1:  Interface between SystemVue and Analytical Graphics (AGI) STK product for multiple-target signal emulation.

As shown in Figure 1, one application of the interface between SystemVue and STK is the ability to do virtual flight testing of a radar system, including DSP, RF impairments, jamming, and interference as an aircraft encounters targets and clutter along a virtual flight plan.

To gain a stronger understanding of the interface between SystemVue and STK, and their application to virtual flight testing, consider the 3D STK simulation scenario of a fighter sortier (Figure 1). It starts at 10,000ft and is detected by the radar. It spot dives down to do low-level terrain following in order to get below the radar- sometimes successfully, sometimes not. This scenario can be reconstructed hundreds of times, with different radar or electronic countermeasure assets in place, by implementing SystemVue. The terrain, aircraft (including 3D RCS), and the radar site characteristics may all be easily modeled and analyzed.


Figure 2: Multiple-Target Signal Emulation Example

In the multiple-target signal emulation example, shown in Figure 2, test entry data is entered through a customer user interface with full customization capabilities. The user does not have to open a simulation schematic. This approach integrates both signal generation and signal analysis. Here, SystemVue creates a radar waveform and passes it through a transmit chain to multiple target models (including jamming and added clutter). The resultant RF waveform can then be input into an arbitrary waveform generator and introduced into a receiver for performance validation. SystemVue also has a tight integration with MATLAB, C++, and HDL simulators, so existing radar algorithms may also be integrated into the scenario. Measurement-based data, such as a jammer profile or measured interference, could also be added into the simulation directly through Keysight test equipment links.

These scenarios can be evaluated in lieu of physical flight testing or, in cases where operational flight testing is unavoidable, they can be evaluated beforehand to ensure they make the most effective use of resources.

Some applications of virtual testing include:

  • Evaluating new jamming techniques or threats
  • Injecting multiple dynamic emitters and targets into scenarios
  • Allowing various types of jamming based on a defined set of criteria for dynamic operation
  • Modeling and evaluating cross-domain effects, such as automatic gain control

Virtual flight testing, made possible by the flexible interfaces between the SystemVue and STK software tools, now offers an economical alternative for R&D validation. This allows measurement-hardened algorithms to be deployed quickly, and any required field-testing to be performed with greater confidence. By moving testing into the lab and away from the field, time and money are spared, while measurement accuracy is improved.

You can read the full article on this topic here and download a free trial of SystemVue.

W1720EP Phased Array Beamforming Kit is a new add-on software simulation for the SystemVue 2016.08 design environment. Keysight EEsof EDA’s W1720EP Phased Array Beamforming Kit overcomes two key challenges facing Active electronically scanned array (AESA) systems:

  • Engineers can easily model highly parallel architectures across multiple simulation domains, including nonlinear RF simulation, as well as a dataflow system level. This allows multiple teams to use the same tool and make architectural trade-offs not previously possible.
  • Engineers can also model the signals as single beams, or maintain access to the individual signals passing through the arrays. This enables multi-function, 3D conformal arrays to be validated in higher-level system scenarios using active signaling between multiple transmitters and receivers.

Who should use the W1720 Phased Array Beamforming Kit?

In typical R&D organizations, many engineering disciplines are required in phased array subsystem design.  The SystemVue Phased Array Beamforming Kit allows RF and baseband teams to use a model-based engineering approach across disciplines. This enables them to perform early R&D validation of phased array system architectures, components and beamforming algorithms, and then continue into hardware test.

System architects can integrate design information from multiple diverse teams, along with test waveforms, to produce winning architectures and proposals

Algorithm and beamforming designers can include RF design information, for more realistic accuracy

RF system architects can directly observe the effects of their RF arrays on high-level beam-level measurements, such as beamwidth, sidelobe levels & nulls, effective radiated power (ERP), and Gain/Temperature (G/T)

System Verifiers can validate scenario-level performance under a range of conditions, as well as automate regression suites, and link to high performance test and measurement equipment




For more detailed application information, refer to:

This DesignCon paper discusses PAM-4 signaling and a new measurement and simulation eco-system. Simulation of PAM-4 signals are done with an IBIS-AMI signal generator, an S-parameter channel model,and remote access software for receiver data recovery. Measured data is from commercially available equipment with specialized waveform processing.

Try a free ADS 30-day trial.



Keysight EEsof EDA's Tutorials in Signal Integrity webcast series is important to Signal integrity engineers who may not have the time or budget to attend continuing education classes on the latest design tools and techniques. This webcast highlights various technologies used for channel modeling, each with advantages and disadvantages, by utilizing real-world FPGA board routing and USB connector design examples. Several state-of-the-art analysis technologies will be highlighted to illustrate the end-to-end modeling of high data rate channels that include ICs, PCB interconnects, vias and connectors.




Register here.

Check out our 6 Q&A collections, with application notes, that target specific topics such as:

• What are the benefits of ADS for SI?
• How to model a high-speed channel?
• What is the benefit of S-parameter simulation?
• How to get TDR impedance from an S-parameter in ADS?
• What are the architectures of the high speed SERDES TX/RX?
• How do you analyze impedance of a PDN?

Signal integrity (SI) is all about the losses and types of signal degradation that can happen along the path (channel) between a transmitter and a receiver. In a perfect world, transmitter communication would instantaneously be heard at the receiver and with no change in the signal. Read more .



Bert Simonovich focuses on signal integrity and other high-speed issues that challenge PCB designers. In this short blog he shares his experience at DesignCon and at the Power Integrity boot camp. If you did not make it to the Power Integrity boot camp you can download the materials from the workshop at:

In this recent technical article our industry experts challenge stand-alone general purpose EM design tools against ADS’s new SIPro and PIPro solutions to overcome SI and PI engineers design limitations while delivering results in a fraction of the time.

My colleague Heidi Barnes has published a great video and a download on "How to Use Fixture De-embedding to Match Signal Integrity Simulations to Measurements." Both the video and the download link are posted on our YouTube channel:



These tools show how to correlate simulation and measurement with a focus on the critical step of either de-embedding the fixture from the measurement, or alternatively embedding a fixture model into the simulation. Useful tips. Thanks, Heidi!

This video shows how design engineers can create parameterized 3D components in EMPro, then simulate them with 3D EM in ADS as part of a larger design, with full access to 3D geometry parameters in ADS.

Try a free EMPro 30-day trial here.