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Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.


This week on Tim’s Blackboard is the “melting trace paradox.”



Unlike other famous paradoxes such as the Zeno’s paradox, where Achilles and the Tortoise are involved, the melting trace paradox is one with a segment of copper trace and a current source, see Fig. 1. 


Fig. 1: The circuit setup for the melting trace paradox.


If you find the equations for power of the trace and the required energy to change the trace temperature, you will find the temperature change of a trace expressed as follows:



whereis the temperature change, and  is the specific heat and mass of the copper and  is the time elapsed.


The equation states that the temperature increases with time. That is, the longer I leave the current source on, the hotter the trace gets. As the temperature reaches the melting temperature of copper, the trace melts.


There is clearly a paradox here. In labs, we know that the temperature of the trace does not increase with no bound, and the trace does not come with a warning label that says “don’t leave current on for too long, trace will melt.” At some point, the temperature of the trace reaches a steady state value.


But how come our prediction is not consistent with our expectation?

Is our math wrong? Or is the world we know broken?

We will now look at the melting trace paradox and find an explanation and solution for it. 


Power and Energy of the Trace

To reconstruct the melting trace paradox, let’s first look the power dissipated by the trace. Assume the trace has resistance  and the current source is delivering  Amps. We can write: 




Since power has the unit Joule per second, we know that the longer we leave the current source on, the more energy,, is consumed:



Next, we will look at how much energy it takes to increase the temperature of the trace.


Increasing the Trace Temperature

Let’s calculate the energy required to increase the temperature of the trace. Recall the definition of specific heat: the amount of heat per unit mass required to raise the temperature by one degree Celsius. Let be the specific heat of the trace and the mass of the trace, we write:



where  is the energy required to increase the trace temperature bydegree Celsius.

Because we have an expression for the energy of the trace, we can re-write the temperature change in terms of energy: 


Melting Trace Paradox     

Here is the energy delivered to the trace:


Here is the temperature change of the trace with given energy:


Replacing  in first equation with  in the second equation , we get:



Putting in the numbers, given 1 A current source and a 1 inch long 20 mil wide copper trace, leaving the current source on for 1 minute results in 1100 oC temperature change, which exceeds the melting point of copper at 1085 oC.

We end up with a melted trace and a frowny face.

What Is Going On?

The assumption we made in calculating the energy generated is that ALL the electric energy goes to heat up the trace. The assumption is wrong for a lab environment.


In a lab environment, we have air to provide heat transfer through convection. However, if we are in space (vacuum) where there is no air for convective heat transfer, the lack of heat transfer traps the heat in the trace and increase the trace temperature with time and finally, the copper trace melts.   


Fig. 2: Air should be included in the setup to correctly represent the lab environment.


As shown in Fig. 2, in most labs, air is present to provide heat transfer through convection, allowing the trace to reach a steady state temperature.


It would be hard to calculate the steady state temperature with pencil and paper. I’ll show you how to find the temperature by performing an electro-thermal simulation with ADS PIPro.  


Electro-Thermal Simulation of the Trace

Entering the same parameters in the ADS PIPro electro-thermal simulator, we can setup two experiments: one with a vacuum and another where air and convection is present.


We would expect the trace in the experiment with a vacuum to have an extremely high temperature, and expect the one with air to reach an equilibrium temperature.


Moreover, with air surrounding the trace, we expect the surrounding of the trace to heat up and have a higher temperature. On the other hand, if the trace is in a vacuum, the surrounding of the trace should stay at the ambient temperature.   


Fig. 3: ADS PIPro electro-thermal simulation of a trace in a vacuum. Since there is no air to allow convective heat transfer, the trace reaches a very high temperature, ~35000 oC.


Shown in Fig. 3, as expected, the trace in vacuum reaches a high temperature, with no heat spreading to the trace’s surroundings. (But if there is no convective heat transfer in vacuum, how does the warmth of the sun gets to the earth!?)



Fig. 4: ADS PIPro electro-thermal simulation of a trace in a lab environment. Since air is present to provide convective heat transfer, the simulated temperature reaches a reasonable value, 56.8 oC


Shown in Fig. 4 is the analysis done with air around the trace. As expected, the air surrounding the trace provides means of heat transfer and allows some energy to escape instead of being all trapped in the trace. Reading from the result plot, we find the final temperature of the trace to be about 56.8 oC.   


The World is Not Broken and Math is Good

After the analysis, we are now sure the world is not broken and our calculations are correct. It is our assumption that needs to be improved. We took the air around us for granted and forgot to include it in our initial analysis.


By performing the consistency tests, we found the solution to the melting trace paradox and now have a better understanding of the thermal aspect of the current source and the trace. 


That's this week's Tim's Blackboard. See you in two weeks!


For more information about how ADS PIPro electro-thermal simulations can solve your paradox, go here:

For an ADS free trial:




Add PDKs to Your Design

Posted by vandduff Employee May 15, 2017

You successfully created a Low Pass Filter in ADS by following my example in the last blog post.  Let’s build off what you know from the Low Pass Filter exercise and learn how to add flexibility to your design, including PDKS and compare an ideal schematic to a schematic with external vendor’s components.


What’s a PDK?

You now want to design a low noise amplifier and need to select what type of process the device needs to be fabricated, whether it’s Si, SiGe, GaAs, or other high frequency manufacturing processes.  A Process Design Kit (PDK) contains active and passive device components with symbols, parameterized layouts, simulations models, and much more for IC design.   A PDK provides both the opportunity to shorten the product design-cycle for high frequency chip design, and the capability to simulate your chip exactly as you expect it before the chip is manufactured.  Some features of a PDK may include:


Schematic Example

Parametric Layout Cells

Design Rule Checks

Simulation Results

Layout Options

For a list of foundries that provide PDKs, follow this link:


Vendor supplied models provide more realistic results, that may include parasitics.  Once your LNA has been created with the PDK of your choice, you can now compare your data to an ideal design by adding your PDK design, and ideal when setting up your plots.  The data can be viewed in several plots, including rectangular and smith chart plots. When setting up your plot, you can plot several traces, which can include any S-parameter measurement, in dB or log.

The lab attached at the bottom shows you how.



What are Cell Views?

Another capability is cell view, which is a way of capturing a design.  It has multiple views and can define a design in that cell using a schematic.  Another way to think about it is within a hierarchy type setting for coding, like pointers in the programming language C.  This capability simplifies what can be viewed in your workspace.   


Check out the attached lab with step-by-step instructions that walk you through the topics we covered: 

  • What is a PDK?
  • Data Comparison
  • What is Cell View?


For other getting started topics, check out our video playlist:

In the past, the pre-manufacture design could be simulated and tested using compliance tools from an EDA vendor. And the post-manufacture prototype could be bench tested using compliance tools from test and measurement instrument vendors. However, because of subtle differences between the two vendor’s independent approaches to compliance, it was almost impossible to correlate the two.


This opened the possibility of the pre-manufacture design passing and the post-manufacture prototype failing, necessitating a time-consuming and expensive design spin. In contrast, Compliance Test Benches leverage the exact same industry-leading Compliance App used on Keysight Infiniium oscilloscopes. Compliance Test Bench mimics a real hardware test bench, and, using a scripting technology called “Waveform Bridge,” emits the same waveforms that the Infiniium app receives when you are testing in your lab. The new approach allows engineers to apply the same set of compliance tests in all three cases: real-time/on-scope, offline/on-scope, and offline/remote.


In Summary, Compliance Test benches can: 


Break the wall between Design Simulation and Lab Measurement

      • Exact same compliance software used for simulation and measurement


Provide probing point where it is not accessible inside the IC chip

  • Equalization takes place inside the chip for SERDES devices
  • It must be simulated to show if the data can be recovered by the receiver

Provide compliance validation before committing to hardware fabrication


Compliance test benches in Keysight ADS are virtual workspaces that can be customized for specific applications. Most of the connection in the design specification are included on these virtual workspaces. You can simply select them and run your simulation. Below is an example of the process to run a simulation to generate waveforms: 


Through this test, you can look at the host side eye diagram as well as the receiver side eye diagram and save the waveform results. Then you can run the exact same compliance application on the virtual scope that you have on your computer/machine. Now, at this stage when the simulation results pass the specification you can have confidence that there is an agreement between your pre-fabrication and post-fabrication results. This way if you find any inconsistency between the two results, you can target the specific problem area. 




More Information

Accurate and efficient modeling is critical to successful design, especially when it comes to the Static Random Access Memory (SRAM) cell, the minimum geometry devices in integrated circuit technology. Modeling such circuits has grown increasingly complex with the advent of nanometer scale process geometries. That’s because increasing process variation makes model stability more challenging.


The latest release of Keysight Technologies’ Model Builder Program (MBP) 2017 now features a SRAM cell model generation package that’s designed to address this challenge head on, by enabling engineers to extract transistor-level and memory-cell models in one MBP session. The user can easily simulate cell-level figures-of-merit, tune model parameters and even compare two memory cell models (Figure 1).

 Comparison of two SRAM cell models, MPB 2017


Figure 1. With MBP 2017, users can easily compare SRAM cell models.


According to Roberto Tinti, Keysight’s Device Modeling Planning Manager, the extraction package came about as a result of a collaboration with a major customer. “Working together we developed a solution that not only reduces modeling iteration but cuts the design cycle as well. It promises to bring many benefits to both existing and future MBP customers.”


Additional enhancements in MBP 2017 include:

  • An enhanced statistical model extraction flow and updated application examples
  • Enhanced extraction flows for BSIM3v3, BSIM4, and BSIM-CMG
  • Updates to the following models: BSIM-CMG 110.0, BSIM-CMG 109.0, BSIM-IMG 102.8, BSIM-IMG 102.7, HiSIM2 2.9.0, HiSIM_HV 2.3.2, HiSIM_HV 2.3.1, HiSIM_HV 2.3.0, EKV 302.00


scripts-based model extraction flow. MBP 2017

Figure 2. Available in MBP 2017 is an updated scripts-based model extraction flow. 


Keysight has also released a new version of its Model Quality Assurance (MQA) 2017 software with enhancements designed to improve modeling efficiency and model quality. MQA 2017 contains a new internal SPICE3 engine that allows users to run quick simulation and quality assurance (QA). It supports the latest compact model versions. Python scripts are also now supported, enabling generation of user-defined Excel tables based on exciting QA results.


"The advanced effects and parasitics in new devices make device modeling more complicated than ever,” said MA Long, Device Modeling Product Manager with Keysight. “With the new internal engine, users can run model quality checks during parameter extraction and uncover potential risks in the early design stage. Support for Python scripts provides the user even more flexibility and functionality in generating tables over the existing TCL and Perl solutions offered."

 compare table generation with python script, MQA 2017

 Figure 3. N/P compare table generation with Python Script as provided by MQA 2017. 


Other enhancements in MQA 2017 include support for Spectre native aging simulation, SmartSpice version 4.26.7.R and Microsoft Office 2016. Unlike traditional manual scripting methods, MQA enables users to check their SPICE models, compare models and generate QA reports in a complete and efficient way.


MBP and MQA are Keysight’s industry-leading device modeling and characterization products. MQA is the industry standard for SPICE model acceptance and sign off, and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses. Information on MBP 2017 and MQA 2017, is available at and, respectively. To apply for a free software trial, go to and


 free trial


There’s a saying around the industry that goes something like “everyone trusts a measurement, except the person who made it, and no one trusts a simulation, except for the person who did the simulation”.  Either way, both have lots of nuances which can impact the end result. Comparing simulation to measurement can be a very difficult task. 


For example, consider the case of a PAM-4 signal through a channel.  By transmitting 2 bits per clock cycle, PAM-4 (Pulse-Amplitude-Modulation, 4 amplitude levels) offers high data rate transmission (56 Gb/s), but there are challenges to implementation; with 4 levels, the traditional eye diagram splits into 3 eyes, meaning less noise and distortion can be tolerated in the channel. 

PAM-4 waveform

Figure 1. PAM-4 waveform.


Because the signal in PAM-4 is more sensitive, an accurate simulation of the channel is essential.  A channel simulation takes the modulated signal and sends it through a physical link (like a cable) to see how the clean signal gets distorted by the channel.   Given the straightforward setup, it may seem simple to correlate simulation to measurement – after all, we can potentially use the same waveform in both simulation and measurement (using an AWG), or measure the S-parameters of the channel directly and use that data in the simulation.  The results should easily correlate, right?  Unfortunately, there are still nuances that can lead to different results. 

Channel measurement setup

Figure 2. Channel measurement setup.


In an eye diagram measurement on an oscilloscope, the signal will likely be preprocessed prior to measurement.  For example, the waveform will be filtered or noise will be injected into the raw waveform.  Modern instruments contain all kinds of tools and functions for data analysis – and these are not always easy to recreate elsewhere (sometimes they’re even proprietary!).


There are also functions in simulation tools that generate eye diagrams– but we wonder what processing is being done in the background?  It’s not always clear.  We could have the exact same signal on the scope and in the simulation, and due to different data processing techniques, get different eye diagrams!  Yikes!

Measured Eye Diagram on Keysight DCA-X 86100D oscilloscope vs. Simulated Eye Diagram in Keysight ADS

Figure 3. Measured eye diagram on Keysight DCA-X 86100D oscilloscope compared to a simulated eye diagram in Keysight ADS.


To eliminate uncertainty, its best to process both waveforms in the same place with the same functions.  But getting measurement data into the simulation environment can be tricky, and getting simulated data onto an oscilloscope could be even trickier.


Wouldn’t it be great if you could just talk to the instrument directly from the simulation tool?  That way, you could configure the instrument, load a waveform, make some measurements, and maybe even return data back to simulation – all without ever leaving your desk.    


Well, now you can!  Using a link between Keysight ADS and Python, it’s possible to transfer data between the simulation and measurement environments, and even control the instrument directly using SCPI commands.  And the great thing is, you don’t even need to know Python to do basic instrument IO.


ADS functions are now available which invoke Python behind the scenes, allowing you to send SCPI commands from ADS to configure a measurement or capture a waveform trace.  All you need to do is load the ADS functions, set up your libraries ( and you’ll be controlling instruments in no time.  The figure below shows how it’s possible to capture a measured PAM-4 waveform directly into ADS with a few simple SCPI commands.

Capturing measured PAM-4 waveform into ADS using SCPI commands

Figure 4. Capturing measured PAM-4 waveform into ADS using SCPI commands.


In the case of the PAM-4 signal mentioned at the beginning, it might be better to process the simulated waveform on the measurement test equipment because the Keysight DCA-X 86100D oscilloscope has lots of built in functionality.  In this case, we can use a Python script to do the heavy lifting: loading the simulation data into the DCA-X 86100D, configuring the scope, processing the eye statistics, and returning the levels back to ADS.  At the same time, you could also measure the physical channel for direct comparison with simulation, using the exact same processing algorithms.  After the Python script has been developed, you can do this all in one step using the ADS Data Link to call the script, transfer the data and receive results back.    

Calling a Python script from ADS to load simulated channel output waveform and compare it directly with the measured waveform.  ADS calls the script and the corresponding PAM-4 levels for both simulation and measurement are returned to ADS.

Figure 5. Calling a Python script from ADS to load simulated channel output waveform and compare it directly with the measured waveform.  ADS calls the script and the corresponding PAM-4 levels for both simulation and measurement are returned to ADS.


For more information watch these videos on YouTube:

  1. Video: ADS Data Link Basics (Part 1 of 3)
  2. Video: Advanced Plotting Using the ADS Data Link (Part 2 of 3)
  3. Video: Instrument Connectivity (Part 3 of 3)

Registered users can view the following application notes in the Keysight EEsof EDA Knowledge Center (register here):

  1. App Note: ADS Data Link Basics
  2. App Note: Advanced Plotting
  3. App Note: Instrument Connectivity


Apply today for your free 30-day full-version trial of Keysight ADS.

FREE Evaluation of ADS | Keysight EEsof EDA 

free trial of ADS

Calling all power electronics engineers! Can you please help me by completing this short survey?

I was excited and intimidated when I took the opportunity to write this blog post for Keysight EEsof EDA.  I had some exposure to what Keysight ADS is and what you can use it for in college – but to write tutorial blogs to assist engineers who design the next satellite that will be launched into space?  That seemed like a daunting task. 


I participated in a training session that walked me through designing a Low Pass Filter and I wanted to share it with you. 

I was able to design this low pass filter in 3 easy steps.


Step 1:  Start up ADS and create your workspace. 

If you don’t have ADS get a free 30-day trial here.


Choose your directory and name your workspace. 


Select only the Analog/RF library, and uncheck all others if needed.  This means that the components from the RF/Analog library will be available for later. 



Name your library, and select the Standard ADS Layers .0001 mil layout resolution.  Make sure everything looks correct, and click “Finish”.


Your workspace is now created!  


Step 2:  Build your schematic.



By expanding to cell view, you can now see that your schematic pops up in your workspace. 




Select the components you need by clicking on the component and dropping it on the schematic page.  You can rotate parts by using the toolbar icon or cursor on or use the cursor to drag the handle on the component.  Connect up the components with the wire button, and don’t forget to ground your circuit! 




To change the values, units, or even the name of your component, double-click the component and make changes as needed.



Step 3:  Set up an S-Parameter Simulation.

Select the “Simulation-S_Param” on the palette and drop it on your schematic area.  Insert the port terminations, and make sure to ground them.



To set up the simulation, double-click the gear on the schematic. Change the step size and frequency range.  I used a step size of .5 going from 1 GHz to 10 GHz.  Click OK, and now you are ready to simulate!


Click the gear (alternatively, use F7), select simulate, and fix any errors that may have shown up.

ADS has a variety of different plots.  I’m going to create a rectangular plot. 



Select the rectangular plot and select which S-parameter measurement you want to use, select your units (S-parameters are usually measured in dB), and click ok. You can zoom in and out with your mouse, and view all with this icon:



Put a marker on the trace, and you can move them around with the red arrows. 




Now I’ve created a low pass filter and plotted an S-parameter measurement. 


That wasn’t so bad, was it?


I skipped a few steps. For a complete set of instructions check out the attached PDF at the bottom of this blog post.


For other getting started topics, check out our video playlist:

If you’re looking for help designing a broadband Power Amplifier (PA), the 3D Smith Chart may be just the answer for you. 3D Smith Charts can be easily generated from Keysight’s Advanced Design System (ADS) software using Python scripts. You don’t even need to know Python. A Data Link with Python in ADS provides a simple way for you to call preprogrammed Python scripts, complete with bi-directional data transfer.


The Cylindrical 3D Smith Chart (also called the "Smith Tube") was pioneered by a team at Baylor University led by Dr. Baylis and presented in a landmark IEEE WAMICON paper in 2014 that introduced the "Smith Tube" in the literature for the very first time (see more references at the end). 


Here are 5 ways a 3D Smith Chart can help you design a broadband PA:


1. It gives you a unique perspective and fast insight into resonance.

LC impedance matching network topology, S22 response

 Figure 1.  This LC impedance matching network topology may at first seem simple to analyze.

s22 response, smith chart


Figure 2. It’s not always obvious, why, for example, a particular resonant inflection occurs in the S22 response such as the one shown at 1.52 GHz.


While an LC impedance matching network for a PA design may seem simple to analyze, understanding why a resonance inflection occurs is not always easy (Figure 1 and 2). If you can get to the root of the resonance, you can exploit it to build a broadband match. A 3D Smith Chart allows you to do just that. By plotting the impedance shift of each individual matching component at each frequency, you can find the cause of a resonance and determine what adjustments are needed to mitigate its effects (Figure 3).

3D Smith Chart, Smith Chart

 3D Smith Chart, Smith Chart3D Smith Chart, Smith Chart
















Figure 3. From these 3D plots, now we can see the resonance around 1.5 GHz occurs due to the impedance from C3, which is “spinning” around the impedance set by the rest of the network.


2. You can create a solid 3D surface. 

3D Smith Chart, Smith Chart, EVM contours, EVM surface3D Smith Chart, Smith Chart, EVM contours, EVM surface














Figure 4. An example EVM surface represented by a set of load-pull contours is shown. By viewing the entire surface in this format, some interesting things stand out that aren’t immediately obvious from the contours.


In PA design, load pull is typically used to sweep a transistor's load and plot contours of constant performance (e.g., output power). Load-pull contours are a flat representation of a 3D surface. Sometimes they are easy to interpret and design with, but using them to interpret the surface topology of complex structures can be challenging. Plotting the entire surface as a 3D solid structure can be very insightful in some instances, for example, finding the minimum EVM region of a PA under a modulated input signal (Figure 4).


 3. You can extend contours to the third dimension.

3D Smith Chart, Smith Chart

Figure 5. A plot of load-pull contours in 3D (with the third dimension being frequency) is shown. 


Suppose you’re trying to design an amplifier to deliver high output power over a broad bandwidth. Typically, this would be done by performing load-pull simulations at several frequencies and then trying to build a matching network to hit the correct loads to deliver the power required for each individual frequency. Using a 1D Smith Chart, this would be a long, difficult process, resulting in so much clutter on the plot that you would likely be unable to make sense of the results. Typically, a designer can only visualize one contour or single frequency set of contours at a time. Plotting the same contours on a 3D Smith Chart “spreads out” the contours and allows you to visualize more information at once (Figure 5).


 4. You can create a surface from cross-sectional data.

 3D Smith Chart, Smith Chart

Figure 6. Another way to visualize the frequency dependent power contours in Figure 5 is to create a solid surface by connecting the contours together in the Z dimension.


With a 3D Smith Chart you can create a solid “triangulated” surface by connecting the contours together in the Z-dimension. This provides you yet another way to visualize the contour data in 3 dimensions. In some cases, contour surfaces are easier to understand than repeated individual contours.


 5. You can plot your 3D matching network and frequency-dependent load-pull contours on the same 3D Smith Chart.

3D Smith Chart, Keysight ADS, ADS Python Data Link Basics3D Smith Chart, Smith Chart
















Figure 7.  The 3D matching network and the frequency-dependent load pull contours are plotted on the same 3D Smith Chart.


By plotting this data together, it’s intuitive to adjust the matching network component values so that the impedance "threads the needle" though the Pout power contour level across the frequency band. An interactive highlight marker in ADS helps you gain insight into what adjustments are needed.


 4 ways to boost simulation data processing using python          Matt Ozalas

These 5 applications of the 3D Smith Chart came from my friend, Matt Ozalas, RF Design Expert. Hear from him yourself in his May 4th, 2017 webcast, Four Ways to Boost Simulation Data Processing Using Python.

 How to Design a Power Amplifier: The Basics

 You might recognize him from his YouTube Series, How to Design a Power Amplifier: The Basics.


 free trial, ADS, Keysight

Apply today for your free 30-day full version trial of Keysight ADS. 


 For more information, see the following IEEE papers:

1. Joseph Barkate ; Matthew Fellows ; Jennifer Barlow ; Charles Baylis ; Robert J. Marks.  "The Power Smith Tube: Joint optimization of power amplifier input power and load impedance for power-added efficiency and adjacent-channel power ratio". IEEE Wamicon, 2015.

2. Matthew Fellows ; Matthew Flachsbart ; Jennifer Barlow ; Joseph Barkate ; Charles Baylis ; Lawrence Cohen ; Robert J. Marks.  "Optimization of power-amplifier load impedance and waveform bandwidth for real-time reconfigurable radar".  IEEE Transactions on Aerospace and Electronic Systems ( Volume: 51, Issue: 3, July 2015 ).

3. Matthew Fellows, Sarvin Rezayat,Jennifer Barlow, Joseph Barkate, Alexander Tsatsoulas,Charles Baylis,Lawrence Cohen. "The bias smith tube: Simultaneous optimization of bias voltage and load impedance in power amplifier design." Radio and Wireless Symposium (RWS), IEEE. 24-27 Jan. 2016.

4. Charles Baylis; Matthew Fellows; Matthew Flachsbart; Jennifer Barlow; Joseph Barkate; Robert J. Marks.  "Enabling the Internet of Things: Reconfigurable power amplifier techniques using intelligent algorithms and the smith tube".  2014 IEEE Dallas Circuits and Systems Conference (DCAS).


You are designing a power amplifier and have a nonlinear device model. You may want to know what load gives the maximum power-added efficiency (PAE) while the device is delivering a specified output power and while it is operating below some maximum allowable gain compression. How do you do this? Andy Howard, a Senior Application Engineer at Keysight Technologies, has created a simulation example that will help you overcome this design challenge. 

The plots below show results in the Load_Pull_Using_Loads_From_File_Data_Mining data display. Andy has specified the desired output power of 32 dBm. The maximum allowed gain compression is increased from 2 to 3 to 4 to 5 dB. The PAE increases from about 49% to > 67%:

This example has two swept-power load pull simulations. Equations are used to interpolate the data to find the load that gives the maximum PAE while delivering a specified power while below a specified maximum amount of gain compression. One of the load pull simulations reads in loads you have specified graphically on a Smith Chart. The other load pull simulation allows you to specify a circular region on a Smith Chart.

To learn more, download Andy's swept-power load pull simulation example on Keysight EEsof Knowledge Center. (a login required)

Interested in Keysight ADS?  

sipro, pipro, free trial

Go straight to the Knowledge Center article (login required): How to Create your own 3D Smith Chart Plots


Engineers surround themselves with the best tools they can find. For the RF engineer, a new tool discussed in the literature recently is the Cylindrical 3D Smith Chart (also called the “Smith Tube”).  This 3D version of the classical Smith Chart allows engineers to explore data in new and interesting ways. It was pioneered by a team at Baylor University led by Dr. Baylis and presented in a landmark IEEE WAMICON paper in 2014 that introduced the "Smith Tube" in the literature for the very first time (see more references at the end). 


The Smith Chart was developed in the 1930’s as a graphical way to transform complex impedances to reflection coefficients.  For an unassuming diagram based on slide rules, the Smith Chart is still enormously relevant in the digital age; in fact, most engineers try to fit so much data into this small circle that we end up with more lines, arcs, and circles than we can ever interpret.  With access to so much data these days, things can get awfully cluttered.  Now, it’s possible to make sense out of more data by adding a third dimension to the classical Smith Chart plot.  For example, on the classic Smith Chart, you can visualize how impedance changes versus frequency.  On the 3D Smith Chart, you can understand how impedance changes versus frequency AND voltage…or gain…or input power, or anything you can imagine!   


To create a 3D Smith Chart, simply take a standard Smith Chart and stack it on an arbitrary Z-axis (Figure 1). The Z-axis can take on any value or scale you desire, such as frequency, power, or transmission line length. The composite plot is then just a stacked set of Smith Charts with each "slice" representing a single classical Smith Chart for a given Z value. 

 3D Smith Chart, Smith Chart

Figure 1. The 3D Smith Chart is analogous to generating a plot in Cylindrical Coordinates, where a cross-sectional plane is represented in polar form by (r,Ɵ) , and the Z-axis is specified in the standard Cartesian Coordinate system.


3D Smith Charts can be easily created using a Python library which can be set up to plug directly into Keysight ADS, which allows you to access this capability to plot and analyze simulation or measurement data.


How to Set Up Your Own 3D Smith Chart


The first step is to set up the ADS Data Link with Python, which provides a simple way to call a Python script from ADS, complete with bi-directional data transfer. Find out how in the video below. Registered users can also view the application note, ADS Data Link with Python

ADS Data Link Basics (Part 1 of 3) - YouTube 


To use the ADS Data Link with Python, you must first install Python Anaconda (available at no charge), and then load the functions into ADS. The ADS and Python functions needed for this setup are available in the workspaces (for registered users). A Data Display with interactive step-by-step instructions is included in the workspace and will walk you through the setup for your particular machine (Figure 2).  

 3D Smith Chart, Keysight ADS, ADS Python Data Link Basics

Figure 2. For most ADS users, this simple data display page should be all that’s needed for setup.


Following setup, you can call Python scripts directly from ADS using previously loaded functions. They can be invoked either from Data Display or from Schematic through a MeasEqn component. To execute a Python script and return what the script prints to the command line, use the following ADS equation:

Eqn Rtn=call_python_script(C"\\PythonScripts","")

Since Python scripts are typically used to process and/or plot data generated from an ADS simulation, you will also need to pass ADS data into Python and then receive data back into ADS from Python. This can be done using the following equation:


ADS_RtnData=call_python_script_IO(PATH to Directory of Python Script, Python Script Name, Data1, Data2, Data3...,DataN)


The above function exports data from ADS into Python, runs the specified Python script (which can access the data), and automatically exports data back to ADS using the Python script—all in one step. Using this function along with a predefined Python script, you can generate a 3D Smith Chart from ADS and plot simulation data on it. The Python scripts used to generate the 3D Smith Chart are provided in the workspace folder ./Smith_3D_wrk/data/Python, provided for registered users. 


Similar 3D Smith Chart plots can be generated from other workspaces. All you have to do is adjust the path string in the function "call_python_script_IO()" to point to the location of the Python folder that has the 3D Smith Chart scripts you are calling.


The above process is ideal if you want to plot points, lines, simple surfaces, and contours using data generated from ADS simulations. If you’re interested in using Python scripting to generate more advanced plots on the 3D Smith Chart; however, then you’ll want to get a better understanding of the Python functions that enable 3D Smith Chart plotting.


Watch this video to see advanced plotting using the ADS Data Python link. Registered users can view the application note, How to Create your own 3D Smith Chart Plots

Advanced Plotting Using the ADS Data Link (Part 2 of 3) - YouTube  


You can see that the 3D Smith Chart offers you unique insights that other standard plotting tools simply cannot, and we've only just begun. Find out so much more in this upcoming live webcast: Four Ways to Boost Simulation Data Processing Using Python.


Four Ways to Boost Simulation Data Processing Using Python


Registered users can view the following resources in the Keysight EEsof EDA Knowledge Center (register here):


Apply today for your free 30-day full-version trial of Keysight ADS. 

free trial, ADS, Keysight



 For more information on the "3D Smith Tube" from the team at Baylor University, see the following IEEE papers:

1. Joseph Barkate ; Matthew Fellows ; Jennifer Barlow ; Charles Baylis ; Robert J. Marks.  "The Power Smith Tube: Joint optimization of power amplifier input power and load impedance for power-added efficiency and adjacent-channel power ratio". IEEE Wamicon, 2015.

2. Matthew Fellows ; Matthew Flachsbart ; Jennifer Barlow ; Joseph Barkate ; Charles Baylis ; Lawrence Cohen ; Robert J. Marks.  "Optimization of power-amplifier load impedance and waveform bandwidth for real-time reconfigurable radar".  IEEE Transactions on Aerospace and Electronic Systems ( Volume: 51, Issue: 3, July 2015 ).

3. Matthew Fellows, Sarvin Rezayat,Jennifer Barlow, Joseph Barkate, Alexander Tsatsoulas,Charles Baylis,Lawrence Cohen. "The bias smith tube: Simultaneous optimization of bias voltage and load impedance in power amplifier design." Radio and Wireless Symposium (RWS), IEEE. 24-27 Jan. 2016.

4. Charles Baylis; Matthew Fellows; Matthew Flachsbart; Jennifer Barlow; Joseph Barkate; Robert J. Marks.  "Enabling the Internet of Things: Reconfigurable power amplifier techniques using intelligent algorithms and the smith tube".  2014 IEEE Dallas Circuits and Systems Conference (DCAS).


Introduced in a separate post, GoldenGate 2017 enhances circuit reliability in RFIC design by checking against electrical (such as voltage and current) and geometrical rules that exist in the PDK and/or rules set by the user. This feature is referred to as safe operating area, or SOA. When GoldenGate 2017 finds out that one of these rules is not met, it will issue a warning in the log file. The RF designer can also track down the failing device(s) in the schematic with the tool’s highlighting feature for an efficient debugging experience.

In analog and RF circuits it is common, for instance, to have different voltage and FET domains, making it easy to have a higher voltage being allowed at some nodes but that same voltage being destructive at other nodes. Traditionally, the check for overvoltage is done manually, which, of course, is not generally reliable and is tedious. The simulation tool can perform this task much more efficiently.

Here is an example where the drain of the transistor sees a slight overvoltage that is not high enough to damage the transistor right away, making the oversight hard to uncover during chip evaluation. However, ignoring this slight overvoltage will cause reliability issues down the road, the type that gives semiconductor manufacturers nightmares. GoldenGate 2017 eliminates these fears. It checks against PDK rules by reading the asserts in the kit and it also allows the user to set his or her own rules to check against, enhancing overall reliability.

GoldenGate 2017 integrates the SOA functionality in a well-designed fashion, making it efficient for RFIC designers to check against rules. Besides printing assert violations in the simulation log file, GoldenGate’s “Violation Display” GUI makes the management of rule violation a breeze by displaying a summary of rule checks. Further debugging is straightforward and is done by expanding the details in the same window. Highlighting the violating device(s) in the schematic is also possible at this stage with the click of a mouse button.

Furthermore, results from sweep runs can be expanded into a separate display window for convenient study and comparison. The tables dynamically update column entries to include only relevant data and to keep the table size manageable.

Do you work on RFIC design and have not tried GoldenGate yet? Download your free trial and discover how this world-class circuit simulation tool can help optimize your design process and resolve your circuit simulation challenges.

GoldenGate, offered by Keysight EEsof EDA, is the best-in-class RFIC simulation tool inside the Cadence Virtuoso design environment. For many years, RF designers have relied on GoldenGate to solve their challenging problems, and have benefited from its robust simulation convergence and fast simulation capabilities to fully characterize their transceiver designs prior to tape-out.

GoldenGate offers powerful RFIC simulation solutions. Here are some of its characteristics:

  • Best-in-Class RF Circuit Simulation
    • Provides the most advanced steady-state (including harmonic balance, time balance, time shooting, and hybrid) and envelope (hybrid time-/frequency-domain nonlinear) solvers for design and verification of RFICs within the Cadence Virtuoso environment
    • Supports all large- and small-signal RF and transient analyses including large-signal stability and full X-parameter modeling and simulation
  • Advanced Analysis Support
    • Offers a wide variety of capabilities, such as Monte Carlo, Corners, and Fast Mismatch & Yield Contributor, to fully explore, analyze, and optimize designs before tape-out, minimizing the time and expense of re-spins
    • Includes a unique transistor-level PLL jitter and noise analysis option
  • Automation and Usability
    • Accelerates design and verification by providing a number of built-in and easily accessible multi-dimensional sweep, optimization, Monte Carlo, and load-pull tools along with simulation management capabilities
    • Automates EVM, ACPR, gain compression, IP3, and load-pull analyses
  • RF to mm-Wave Design Support
    • Provides access to ADS Data Display with dedicated RF templates and adsLib with over 150 RF distributed-element library components
    • Handles large S-parameter blocks with Multi-Threaded Convolution
  • Wireless Standard-Compliant Design
    • Enables scalable system-level solutions from RF architecture exploration through end-to-end verification with links to SystemVue and Ptolemy
    • Verifies full radio functionality using Keysight's comprehensive library of standard-based wireless verification intellectual property (IP) to accelerate the validation of complex RFICs; wireless libraries for 5G, Bluetooth, LTE, WCDMA, WiMAX, DTV, etc.


Keysight EDA has just released GoldenGate 2017, which introduces the following new features:

  • Safe Operating Area (SOA) – With SOA, GoldenGate 2017 enhances circuit reliability by automatically ensuring all devices operate within their safe operating areas – electrical or geometrical rules set by the PDK and/or the user. GoldenGate 2017 produces appropriate warnings, and highlights the failing devices in the schematic, simplifying the debugging process. This feature replaces tedious and unreliable manual checks. SOA is covered in more detail in a separate post.
  • TSMC Model Interface (TMI) – The use of the new and fast TSMC silicon processes – 16nm FinFET or later – which all require TMI support, makes it possible to design mm-wave circuits with silicon. Doing so enables the mass production of transceivers employed by systems adhering to the upcoming communications standards. Now that GoldenGate supports TMI, users can take full advantage of many of GoldenGate’s strengths, such as robust simulation convergence and fast simulation speed, while designing the latest and greatest circuits. It is worth mentioning that GoldenGate’s implementation of TMI also supports the circuit aging feature of TMI.
  • Simulation Speed Improvement – GoldenGate 2017 significantly improves its envelope transient simulation time and further establishes itself in the efficient simulation realm by introducing 4x parallel threading. Relatively long envelope transient simulation runs benefit the most, and that is where speed matters the most. The following table showcases a few sample envelope transient test runs.


Test Case

Wall Time prior to GoldenGate 2017

GoldenGate 2017 Wall Time

Wall Time Improvement

White Noise, ET




Power Amplifier ACPR, ET 3




Unit NPort Recurs Var Step, ET




Level 3 ET





  • New and Updated Model Support – GoldenGate 2017 adds support for the following models: BSIM-IMG 102.6.1, 102.7, and 102.8, BSIM-CMG 106.1, 107, 108, and 110, BSIM-CMG Level = 72, BSIMSOI 4.4, CMC Diode, MOSVAR 1.3, Leti-UTSOI 2.20, HiSIM HV 2.10 and 2.3.1, HiSIM 2.9.0, HICUM L0 1.32, and HICUM L2 2.34


   GoldenGate is part of Keysight's RFIC solution that also includes Momentum for 3-D planar electromagnetic simulation and Advanced Design System (ADS) for linking the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow. GoldenGate 2017 is fully compatible with the following Cadence versions:

  • IC 5.1.0 and all subversions
  • IC 6.1.5, 6.1.6, 6.1.7, and all subversions
  • ICADV 12.1 and 12.2


   Do you work on RFIC design and have not tried GoldenGate yet? Download your free trial and discover how this world-class circuit simulation tool can help optimize your design process and resolve your circuit simulation challenges.

A statistical simulation technique has become popular for the design and analysis of high-speed signals. Especially where accurate prediction of random jitter is important, such as in the measurement of eye opening at ultra-low BERs. In this DesignCon 2017 paper published by my colleagues Hee-Soo Lee, Cindy Cui, Heidi Barnes, and Luis Boluna, you can learn about advantages of the statistical approach for the accurate prediction of random jitter at ultra-low BER, and the limitation of this approach due to SSN (simultaneous switching noise). This paper proposes a solution that extracts the mask correction factor from the voltage noise calculated from a transient simulation, then uses it for accurate prediction of eye height and eye width calculation in the statistical analysis. Measurement data is provided to validate the approach.


Crosstalk and Delta-I noise are significant noise sources for DDR4 designs and are known as simultaneous switching output noise (SSON), or SSN. For DDR4 systems (up to 3200 MT/s), the Inter-Symbol Interference (ISI) and Random Jitter (RJ) induce timing margin uncertainties, which cannot be ignored because the shrinking unit interval (UI). In order to take into account the RJ and ISI effects accurately, JEDEC introduced the new DQ receiver compliance mask at 1e-16 BER in the DDR4 specification.

The new DQ compliance specification requires an eye opening at an ultra-low BER level, 1e-16, which poses a new challenge to simulation-based design methodology. The traditional simulation approach was based on SPICE-like time domain simulation technologies.

As you may find from Figure 2, the eye shrinking induced by inter-symbol interference (ISI) and random jitter (RJ) is relatively small at a low data rate (800 Mb/s). However, the timing margin decreases by 9% UI (15ps) from 103 to 1016 bits because of ISI and RJ effects at 3200 Mb/s data rate system. This proves that time-domain simulation, even with several thousand bits, is far more inadequate to accurately predict the eye opening at 1e-16 BER level.


We can get the ultra-low BER contours at a fraction of the time required for SPICE-like time-domain simulation methods by using the statistical analysis method. The dilemma is that the statistical simulation has to be used for
calculation of the ultra-low BER contours but the Delta-I noise contribution for SSN is not taken into
consideration.To address this challenge, a practical and efficient SSN induced jitter and noise model extraction
method is proposed in this paper. The extracted jitter and noise values will be used to correct the
eye height and width calculation at a certain BER level as well as the JEDEC DQ compliance mask
to reflect the eye-margin correctly. This methodology improves the accuracy of DDR4 statistical simulation, by using the mask correction factor. The extraction process of mask correction factor is relatively simple and quick but still, delivers reasonable accuracy while overcoming the limitation of the statistical simulation approach with the SSN induced time variant Delta-I noise. The validated correlation between measured and simulated data as it is discussed in this paper proves that this methodology can be effectively used for DDR4 designs. 


If you want to learn more about a practical and efficient SSN induced jitter and noise model extraction
approach and the measurement process, download this 
DesignCon paper here: 

SIPro, PIPro, free trial

PCI Express Gen3 (PCIe Gen3) specifies a high-speed differential I/O interconnect that runs at 8.0 Gbps. It has many benefits, and it also presents a critical challenge. PCIe, using high-speed 8-Gbps serial links, can suffer from a large array of physical phenomena and this can lead to excessive EMI emissions in large systems. Fortunately, there is a way to overcome this challenge and ensure high signal quality in PCIe Gen3 serial channels. The solution involves the use of signal integrity analysis, compliance testing, and a PCIe interface simulation methodology that relies on IBIS-AMI models to account for different channel parameters—all of which can be accomplished using Advanced Design System (ADS) software (Figures 1 and 2).

 SI analysis, PCIe Connector, PCIe Gen3, eye diagram, Keysight ADS

Figure 1. During SI analysis, the PCIe connector, 8-lane data bus and package are simulated using an EM solver. S-parameter data is then extracted and factors like impedance matching and propagation delay are analyzed. Finally, all data is re-combined and a Pseudo-Random Bit Sequence (PRBS) is generated at a bit rate of 8 Gbps. The simulation setup and result of a transient analysis with PRBS random data input for the channel is shown here.


PCIe channel, PCIe 3.0, Keysight ADS

Figure 2. Compliance testing ensures products are interoperable. It validates that the PCIe channel is compliant with the PCIe specification. Shown here is the eye and jitter measurement in ADS on a PCIe 3.0 transmitter transaction bit.


Want to learn more about this approach and what it entails? Check out the article, Ensuring High Signal Quality in PCIe Gen3 Channels, by Keysight Technologies’ Anil Kumar Pandey in the Signal Integrity Journal.  


SIPro, PIPro, free trial


Python is a programming language that lets you work quickly and integrate systems more effectively. It’s been used in many areas such as Statistical Analysis, or Artificial Intelligence; and it is also very useful in Device Modeling.

Today we are going to introduce the Python integration with Keysight IC-CAP device modeling platform (version 2013 and up), where we can readily use Python to gain additional productivity.

We will go through one example to get the MOSFET threshold voltage (Vth) using Python, but first, let’s take a look at what version and libraries are supported in IC-CAP.


Python Version



   Windows and Linux IC-CAP support


Supported Libraries:


 The built-in IC-CAP APIs dedicated to device modeling.


The fundamental package for scientific computing with Python.


Goes hand-in-hand with NumPy, is an ecosystem for mathematics, science, and engineering.


A Python 2D plotting library which produces publication quality figures.


Python bindings for the Qt to create innovative devices, modern UIs.


“iccap” is a built-in Python module in IC-CAP which provides objects (such as Model, Dut and Input) to interact with IC-CAP data structures. Below is the Python API tree, and more detailed API explanation and Python tutorial can be found in IC-CAP’s user manual.

Now, let’s take a look at how to use Python to do data analysis, such as to calculate Vth from an IdVg curve in IC-CAP. The example is based on the built-in model file: $ICCAP_ROOT/examples/model_files/mosfet/nmos3.mdl.

Figure 1. Vth algorithm using Icon method with deltaW(xw) and deltaL(xl)

NOTE: There are many possible methods to calculate Vth 1. For today’s example, we will use the constant current approach1,2, which is widely used in industry due to its simplicity.

The steps are:

  1. Open the “nmos3.mdl” file from ICCAP Main window.

  2. Open the nmos3 model window, as shown below:

  3. Switch to the “Macros” tab, where we see some pre-defined PEL macros.

  4. Now, we can add a macro via the “New…” button at left, name it “cal_vth”, and set the Macro type to be “Python (Local Namespace) option, as highlighted below:

    The Python script shown above calculates Vth from the IdVg@Vb=0 curve from the large DUT.
  5. On line 23, we used a Python class called VthCon in which the Vth extraction algorithm is implemented. This calculation can be implemented in the IC-CAP UI, or one can create and refer to an existing Python script created outside of IC-CAP. We will show both methods.
    1. Create the VthCon Python Class in ICCAP
      Use “New…” to create another macro, name it VthCon, and add the content, as  shown below:

      After the class VthCon and calculate functions have been defined, click on the “Execute” button so that the class gets registered in ICCAP memory and can now be used by other Python macros. 
      To see this in action, go back to the “cal_vth” macro, click the “Execute” button, and see the Vth value printed in IC-CAP’s Status window.

    2. Refer to a Python Class defined outside of ICCAP
      If we have existing Python files that have utility functions or Python classes defined, we can certainly use them directly without re-creating them again in ICCAP.
      This approach requires we set an OS environment variable called ICCAP_USER_PYTHON_PATH to the directory where those python files are located, as shown below:

      Python source code files are then stored in the directory specified:

      If files were newly added to that directory, you will need to restart IC-CAP, load the nmos3.mdl again and go back to the Macros tab to access these programs. To test this, add another new Macro, name it ‘cal_vth_use_external’, and again set the Type to be Python (Local Namespace).

We now can import the class or functions from the external files by adding the 2 lines highlighted below to the top of the macro. The remainder of code is the same

as for the cal_vth function we saw above.


from iccap_vth import VthCon

from iccap_util import *




Please contact us to download the IC-CAP model and Python files used in this example.

Thank you!