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A new video by Wolfspeed demonstrates how the Wolfspeed ADS process design kit (PDK) is configured to work with the Keysight ADS electrothermal simulator to co-simulate electrical and thermal performance together.


Figure 1. Wolfspeed’s process design kits work with Keysight Technologies’ ADS electrothermal simulator to co-simulate electrical and thermal performance together.


The electro-thermal simulation capability allows designers can see the impact of thermal effects on circuits while still in the design stage, and account for those effects early on in the design process. This becomes especially helpful when using a high power density technology like SiC or GaN.


Wolfspeed is the largest SiC and GaN wide bandgap Power and RF fabrication facility worldwide. They are the leading supplier of SiC and GaN materials, providing lighter, faster, and more powerful devices to industry experts around the world. Wolfspeed offers non-linear, scalable GaN HEMT models for MMICs, as well as full PDKs for Keysight Technologies’ Advanced Design System (ADS).



Figure 2. Wolfspeed’s video shows allows designers can see the impact of thermal effects on circuits while still in the design stage, and account for those effects early on in the design process.


Because of their dedication to a more energy efficient future, Wolfspeed takes the lead in the innovation of power and wireless systems with wide-band semiconductors. These materials enable devices to function at higher voltages, frequencies, and temperatures, allowing for broader use of alternative energy devices. The electro-thermal simulator accounts for significant thermal effects that often occur with these increasingly popular materials.

You can watch Wolfspeed’s new video below. They walk you through the process of co-simulating electrical and thermal performance using the Wolfspeed PDK.



To learn more about the ADS Electro-Thermal Simulation Element, watch this 30-second video or visit



FREE Evaluation of ADS | Keysight EEsof EDA 

Keysight’s latest release of SystemVue 2017 is the industry’s leading simulation platform for system design and verification, giving designers the earliest possible head start in entering the high-margin 5G market.


With its unique 5G functionality, SystemVue 2017 now makes it possible for 5G cellular system, RF component, and chipset vendors to create pre-5G-compliant reference designs. Designers can start pre-5G now and continue forward into the final 5G New Radio (NR) standard as it becomes available.

 5G verification library

Figure 1. SystemVue 5G Verification library merges Verizon and KT 5G wireless standards with 100GHz mmWave channel model and adaptive beamforming needed for 5G cellular base stations and handsets.


The new software adds functionality not possible with other 5G electronic design automation (EDA) solutions on the market today. Unique features include the ability to incorporate S-parameters of off-the-shelf phase shifters and attenuators, and X- or Sys-parameters of nonlinear amplifiers and mixers.


In addition to its powerful 5G and phased-array functionalities, SystemVue 2017 offers three important updates designed to enable early electronic product designs with high margin and volume potential for emerging standards:


  1. New Automotive Radar library, which features unique pedestrian channel models with micro-Doppler detection of moving pedestrians
  2. NB-IoT or LTE-Advanced Pro, which is an enhancement to the LTE-Advanced baseband verification library for validating Narrow-Band Internet of Things (IoT) product designs
  3. 802.11ax enhancement has also been added to the WLAN baseband verification library for designing even higher speed WiFi networking

 Phased Array Architext

Figure 2. SystemVue 2017 Phase Array Architect allows accurate RF S-, X- and Sys-parameters of amplifiers, phase shifters, attenuators to be used in Phased Array Antenna system design.


5G communications systems architects can quickly iterate and validate their 5G designs, allowing developers to cross traditional Baseband and RF boundaries in order to innovate the physical layer of next-generation communications systems.


For more information on SystemVue 2017, go to




Get your free trial today!



A high-quality device model captures device behavior across geometry (W/L), temperature (T), drive voltage (Vdd), among numerous other input conditions. How much time do we spend trying to achieve a good fit across all these axes? What if we could easily bring up graphs of all key device targets such Vth (Threshold Voltage), Idsat (Drive Current), GM (Transconductance), and their variations across these dimensions?  We could then monitor them in one place, and tune or optimize model parameters while observing the agreement between measured and modeled data.  With Keysight’s Model Builder Program (MBP) 2017, we can achieve this goal. In this note, we are going to go through a couple of examples to show how MBP Script makes it possible to monitor device targets across the entire matrix of input conditions.


First, let’s look at the Threshold Voltage (Vth) variation as we vary device width (W) and length (L) on 4 sides of the W/L matrix, as shown below. 

Figure 1. Four sides of the W/L matrix for evaluation of Vth variation


The 4 sides of W/L space define the boundaries of modeled device sizes provided by a given semiconductor technology. A customer may use a geometry outside of this space, but will then need to re-target the model parameters for this unusual device.


Vth is the key device parameter of any transistor device, be it BULK, SOI or FinFET.  It defines when a transistor transitions from off to on.  If the Vth has been well modeled along the 4 sides of the W/L space, then we have good confidence that the model will work over the entire W/L plane. Both short and narrow channel effects will be covered.

By placing Tasks in sequence, a user may define a real modeling flow to be executed automatically.  A “Task” is object to represent a step in a flow, and is represented by a blue icon in the flow panel, as shown below in figure 2.  With Tasks, a modeling engineer can group modeling building blocks to extract the next logical group of device parameters.  In MBP, we may create a new Task button, as shown below, called “Display_Vth_Scaling_4_sides.”  By  clicking on this button, we can define and display the related graphs.


Figure 2. Display Vth W/L scaling plots by Task button clicking


In figure 2, we plot Vth in a 2x2 layout, where each quadrant represents one side of the W and L scaling space.  The solid represents simulated data and the square represent measurements.  The MBP tool is now ready for model tuning or optimization.


To create this beautiful matrix of graphs, we need to create a new Task from MBP Script window and name it “Display_Vth_Scaling_4_sides,” as shown in figure 3.  In the newly created Task, in its Plot Select tab, click the “Add Plot” button to add these 4 plots.  We may populate the “Plot Name” using 2 of the predefined plot groups “vth_l_vbs” and “vth_w_vbs.” In the “filter define” field, we may filter the data based on desired input conditions, like “w=max(w)”.  The filter definition is highlighted in green for the first plot where vds=abs(min(vds)) && w=max(w). In other words, we filter the data for the absolute minimum Vds, and maximum W input conditions. 



Figure 3. Create a Task by grouping Vth W/L scaling plots


MBP provides the most commonly used device targets, including Vth, Gm, Idsat, Idlin, etc. as well as common plot templates like the scaling graphs over W, L, T and Vdd.


One powerful plot type shows how well the model has been fitted across input conditions like geometry.  This is called an “Error Data Grid” plot.  In figure 4, we present the RMS error of device targets Vth and Idsat in our 2-dimensional geometry plane. However, we can choose pairs of input conditions to study, for example:

  • W and L
  • W/L and T
  • W/L and VDD


Figure 4. RMS Error plots of Vth and Idsat across W/L plane.


When tuning model parameters, we can observe the RMS errors update on the fly. For example, slightly different model parameter settings lead to the following Error Data Grid plots:

Figure 5. another state of the RMS Error plot of Figure 4.


The numbers are color-coded for quick and easy reading.


In figure 6, we illustrate how to create these incredibly useful Error Data Grid plots. In MBP’s Script window, we choose our device target (Idsat), specify the X and Y axes as ‘w’ and ‘l’ below, coloring for various RMS error ranges, etc. We can even add more targets to our Error Data Grid plot.


Figure 6. ErrorDataGrid plot creation


These newly created plots can be integrated in the Flow as another Task button, as shown below:

Figure 7. Display RMS Error plots by Task button clicking


Every Task object has a few properties of which “button mode” is one.  When the task is in button mode, then when you click it, it executes just that code to do an action, like extracting a group of parameters.  When the task is not in button mode, clicking on it has no immediate effect.  Rather, it marks where the flow may resume. 


By monitoring a model’s performance (RMS error) across all input conditions, MBP provides a high-level view of the model in real time.  Our modeling engineer may enjoy the peace of mind that the device model has been done thoroughly and accurately.


Please see the attachment below.  We have attached an example project that includes:

  1. demo data files
  2. demo model files, initial version and final version.
  3. script file that defines the flow Tasks and ErrorDataGrid plots


For more details about how to customize device targets and plots and how to customize the flow, please refer to the MBP Script tutorial.




You have a waveform that was generated in MATLAB. How do you use that waveform as the source for a circuit in Genesys?


Keysight’s RF/Microwave Synthesis and Simulation Software, Genesys understands MATLAB. The full-featured MATLAB script debugger in Genesys enables you to develop error-free, fully compatible equations for data processing, simulation, and analysis. Genesys equation pages use MATLAB, so it is very easy to generate MATLAB waveforms in Genesys. You can paste MATLAB code directly onto a Genesys equation page to create any waveform.


Figure 1. You can easily import a MATLAB waveform into Genesys, and use that waveform as a source for a circuit.


Genesys Understands MATLAB

Running the MATLAB code in the equations page allows you to see and verify the waveform. Here, the waveform is stored and plotted in a variable called “PulseTrain”. The user will run the Equations first, and then the variable will be used by the source in the Genesys design.


Figure 2. The waveform is stored and plotted in a variable called “PulseTrain.” (Click image to zoom.)


How to apply the waveform to a circuit

In order to apply the waveform to a circuit, use a Custom Voltage source which allows us to specify a variable, PulseTrain, for the V parameter.


Figure 3. The variable PulseTrain is available for the source to use in the Genesys design.


From here, all that’s needed is to set up the Transient simulation for the desired time step and stop time. Run the simulation, and see the results below.





To use a waveform developed in MATLAB:

  1. Paste the MATLAB code that creates the waveform into an Equation page in Genesys.
  2. Assign the variable containing the waveform to a Custom Voltage source on the schematic.
  3. Run a Transient simulation.
  4. View the results.


Check out the related application note here.





Click here for a free trial of Genesys.

Having trouble getting started with your next circuit design? Keysight EEsof EDA’s YouTube channel is filled with “How To” videos and examples to help you with your complex designs. In each video, Keysight engineers walk you through the steps while also covering the fundamentals of each topic. At the end of each video, you can download the workspace to help get you started on your own projects. These five videos are a must-see for anyone working with Keysight ADS.


1. How to Design an RF Power Amplifier: The Basics

This video shows how power amplifier circuits work. If you are new to high-frequency power amplifier circuit design, this is the place to start. If you are an experienced designer, this video provides unique insights into the fundamentals that you may not have seen before. There is also an entire playlist dedicated to this topic on our YouTube channel.


Questions answered include:

  • What is AC power?
  • How is AC power generated and dissipated?
  • What topologies are convenient to use for power amplifier circuits?
  • What is a loadline and how can this be used to design a power amplifier?



2. How to Design for Power Integrity: Selecting a VRM

This video is one of a three-part series in Power Integrity tutorials. There are many factors to consider when selecting a VRM (Voltage Regulator Module), and this video covers two: Output Impedance and PSRR (Power Supply Rejection Ratio). This video uses measurement-based simulations to show that current mode topology is the best choice for flat impedance VRM.


Questions answered include:

  • What factors should I consider when selecting a VRM?
  • Why is flat impedance the PDN design goal?
  • Why is VRM selection not arbitrary?


3. How to Use Fixture De-embedding to Match Signal Integrity Simulations to Measurements

This video provides a quick 4-step process to show how to de-embed a fixture from a measurement to validate a PCB channel model, and then how to embed the fixture with the model to do a direct compare of simulation to full-path measurement both in the frequency domain and time domain.


Questions answered include:

  • How can I match SI simulations to measurements?
  • How can S-parameters simplify the problem?
  • What is the best process to solve this problem?


4. How to Design Phased Array Systems

This video discusses the most important considerations for phased array system design, especially popular for 5G. It begins with the basics of phased array design, then covers 4 key parameters of phased array architecture. After watching this video, you will be able to download the simulation tool, SystemVue, to perform your own phased array modeling and simulations.


Questions answered include:

  • How does a phased array work?
  • What are the key elements of phased array architecture?
  • What factors influence the far field pattern?




5. How to Understand 5G: Beamforming

This video guides you through what kinds of multi-antenna system architectures are being researched for the next generation 5G standard. It provides examples with end-to-end link level simulation and demonstrates key technical issues of different multi-antenna beamforming system design under mmWave channel environments.


Questions answered include:

  • How does beamforming work?
  • How can I model and simulate for key multi-antenna systems architectures?
  • Is hybrid beamforming too good to be true?
  • What is the 3GPP channel model for mmWave frequency band?




These are just five of the growing library of “How to” videos from Keysight EEsof EDA. Apply for a free trial of ADS or SystemVue to get started on your own designs.




Click here to apply for a free trial of ADS.


Keysight EEsof EDA is introducing a new set of tools for 5G, starting with pre-5G modulation analysis. This new technology is geared toward innovators with 5G testing in mind.  The 89600 VSA software provides comprehensive analysis capabilities for pre-5G signals based on the Verizon 5G open trial specifications.  With the standardized pre-5G technical specifications, engineers are already taking steps toward signal analysis.


vsaFigure 1. 89600 VSA users can observe pre-5G uplink and downlink physics layer measurements based on the Verizon 5G specifications. This example shows a downlink signal with 8 component carriers.


5G networks promise faster speeds, higher data rate, easier connectivity, and better network performance. Pre-5G allows users to experience certain 5G network elements while ensuring compatibility with their current 4G and LTE platforms.


Keysight’s latest 89600 VSA software helps break through the complexity of pre-5G, and will do the same for 3GPP 5G New Radio (NR). 3GPP 5G NR is the emerging global 5G standard. It is expected to be included in Release 15 of the 3GPP standard, which is due out later this year. With Keysight’s new 89600 VSA software release, early adopters can design and verify performance to the draft specification now, before it is published. Its extensive set of tools for demodulation and vector signal analysis enable you to explore virtually every facet of a signal and optimize even the most advanced designs.  


Figure 2. The 89600 VSA software will unify and accelerate the development process by providing
frequency-, time-, and modulation-domain analysis results in a single measurement.


The 89600 VSA software will unify and accelerate the development process by providing frequency-, time-, and modulation-domain analysis results in a single measurement. Users can observe pre-5G uplink and downlink physical layer measurements based on the Verizon 5G specifications. The 89600 VSA software is a vital and effective tool that will help blaze the trail to the 5G frontier.



The latest 89600 VSA software has over 100 recorded demo signals available for trial users. Discover the fundamentals of pre-5G air interface parameters, physical channels and signals.


Read the technical overview for more information on pre-5G signal analysis.


See the vast capabilities of the 89600 VSA Pre-5G Modulation Analysis in this four-minute video tour.



You can now jump start your 5G development for Verizon 5G, and continue for upcoming 3GPP 5G NR with a free trial of the 89600 VSA software.


“The important thing in science is not so much to obtain new facts as to discover new ways of thinking about them.”-Sir William Henry Bragg Inventor of X-ray spectrometer, Nobel Prize for Physics, 1915


Much like Sir William Henry Bragg stated, often, the recipe for new discovery entails new light, so elements can be viewed in a fresh perspective.


This week on Tim’s Blackboard, I will start with the motivation for Fourier to introduce his series, follow by his unintentionally visit to the frequency domain, and end with how the new frequency domain view helps us understand the root cause of eye closure. 


Fourier and “The Analytic Theory of Heat”

Whenever frequency domain is in a conversation, there is no escape from mentioning the name of this famous mathematician and physicist: Joseph Fourier.


Fig. 1: Jean-Baptiste Joseph Fourier. Image credit:


Although well-known for Fourier Series and Transform, in his 1800’s publications, the French-born scientist in Fig. 1 was originally analyzing heat flow.  


To solve the heat equation in a metal plate, Fourier had the idea to decompose a complicated heat source as a linear combination of simple sine and cosine waves, and to write the solution as a superposition of the corresponding eigen-solutions. Nowadays, this superposition or linear combination is known as the Fourier Series [1].


Fourier Series: Unfamiliar Yet Familiar

Although trying to represent a complicated function with linear combinations of sine and cosines might sound foreign, the decomposition of a complicated element into simpler sub-elements is a familiar idea.


In his lecture on Fourier Series, MIT Professor Dennis Freeman cleverly illustrates the similarity between Fourier Series and the Cartesian representation of an arbitrary vector in 3D-space [2].


Fig. 2: An arbitrary vector in 3D-space.


Shown in Fig. 2 is an arbitrary vector in 3D-space. Without additional coordinate information, our view of the vector is a geometric one: a line. However, as soon as we place the vector in a coordinate system, the vector geometry translates to vector magnitudes and directions. In a Cartesian system, there are three different components: one in x-direction, one in y-direction and one in the z-direction, as demonstrated in Fig. 3.


Fig. 3: Representation of an arbitrary vector in 3D-space in Cartesian coordinates. The original vector is separated into three components of various magnitudes in different directions.


The concept of Fourier Series is extremely similar. In Fourier Series, one deconstructs a periodic function into sines and cosines of different frequencies. The different frequencies of cosines and sines are analogous to the different directions in the Cartesian coordinates.


Take a classic ideal square wave for example. Fig. 4 shows the comparison between representing a vector in 3D-space and expressing a square wave with Fourier Series.


Fig. 4: Comparison between a vector in 3D-space and an ideal square wave expressed in Fourier Series. The sine waves of different frequencies correspond to the different directions in Cartesian coordinate system. 


It is important to note in Fig. 4, the “…” in the Fourier Series expression indicates an infinite sum of sines with only odd harmonics. Mathematically, we write



Unlike the vector in 3D-space, where only three magnitudes and directions are needed to recreate the vector, we need infinite number of magnitude and directions to truthfully represent the ideal square wave in Fourier Series.


But Tim, what if instead of infinite number of odd harmonics, I only have the first 10?


In ADS, there is a Vf_Square source that lets you experiment with the number of harmonics you desire to be in the Fourier Series. The result of the simulation is in Fig. 5.


Fig. 5: ADS simulation result of including only the first 10 odd harmonics in the square wave.


Stepping into Frequency Domain

Writing a function in the form of Fourier Series gives us a fresh perspective. Specifically, by looking at the Fourier Series construction of a function, we are able to visualize the frequency components present in the function and the strength of each frequency component.


Let’s revisit the ideal square wave expression, the Fourier Series shown below has both “direction” and “magnitude.”



Because the multiplication factor in front of ω0 indicates the frequency of the sine wave, we plot the factor, n, on the x-axis. For each nth harmonic, there is a specific magnitude that goes on the y-axis. Fig. 6 illustrates the parameters we are plotting.

Fig. 6: Illustration of what goes on a frequency domain plot. On the x-axis, we plot the harmonics, and we plot the magnitude on the y-axis.


Fig. 7 displays the log-log plot of frequency domain spectrum up to the 100th harmonic of the sine wave component that makes up the ideal square wave. The 1/n relationship of the magnitude and harmonic is made clear in a log-log plot.  


Fig. 7: Frequency spectrum of an ideal square wave up to the 100th harmonic. The magnitude of the harmonics is inversely proportional to the order of each harmonic. 


Extension of Fourier Series

Indeed, Fourier Series is very useful when it comes to representing a periodic waveform. Nonetheless, one major limitation of Fourier Series is the assumption of periodic waveform.


Let’s take the impulse response of a channel for example. Fig. 8 is the waveform of a channel we investigated in Dirac Delta Misnomer. The impulse response is NOT a periodic function. If I am interested in the impact of the channel on different frequency components, I would need a way to transform the aperiodic time domain response to the frequency domain.

Fig. 8: Time domain impulse response of a channel is not a periodic function.


In the next post, I will show that with the help of Fourier transform, an extension of Fourier Series, I can convert the time domain impulse response to the frequency domain insertion loss, as shown in Fig. 9.


Fig. 9: Frequency domain representation of the time domain impulse, also known as the insertion loss.


Because the insertion loss plot gives us valuable information on how each frequency component is affected by the channel, we can then identify the root cause of eye closure.



As Sir William Bragg points out, new discovery requires a new point of view. There is no doubt Fourier’s approach to the heat equation is a novel one.


By using Fourier Series, we examine the ideal square wave through the frequency domain looking glass. In the next weeks, we will see how we apply Fourier transform to understand the root cause of eye closure.    


That's this week's Tim's Blackboard. See you in two weeks!


Experiment with the square wave source: 



Wikipedia contributors, "Fourier series," 9 August 2017. [Online]. Available:


D. Freeman, "6.003 Signals and Systems," Massachusetts Institute of Technology: MIT OpenCourseWare, Fall 2011. [Online]. Available:


Demands for faster data speeds and more reliable services are at an all-time high. 5G is predicted to meet these demands, and much more. Although 5G is currently still in the planning stages, researchers are uncovering solutions that were previously thought impossible. Until recently, mm-waves have been viewed as unsuitable for mobile communication. However, new research has shown that propagation issues can be overcome, with help from mm-wave small-circuit designs.


Plextek RFI is a leading company in 5G design, specializing in the design and development of RFICs, MMICs and microwave/mm-wave modules. The designers at Plextek RFI manage their own RF On Wafer (RFOW) test facility, providing several leading foundries highly developed design services. Their designs are used in a wide range of applications from test instrumentation to infrastructure equipment and the latest mm-wave 5G systems.


Plextek RFI also has a growing archive of video tutorials on various design topics in a wide range of applications from test instrumentation to infrastructure equipment and the latest mm-wave 5G systems.

The most recent video tutorial provides a visual demonstration of the design, layout, and performance of a Dual-Band 5G Power Amp using Keysight ADS.


dual band layout

Figure 1. Full layout of a mm-wave 5G dual-band power amplifier.


Dual-band power amps are vastly popular in proposed 5G designs due to the wide range of frequencies used in 5G applications. They perform almost as well as two single-band PAs combined, as they are capable of electronically switching their operating band between the 26GHz and 32GHz 5G bands. They are small, inexpensive, and with ADS, easy to design.


ADS schematic of dual-band PA

Figure 2: ADS schematic of three-stage dual-band power amplifier.


s-parameters pf PHEMT switch transistor

Figure 3: S-parameters vs. frequency of a pHEMT switch transistor, used to alter effects of transmission lines in low and high bands.



Watch the 20-minute tutorial video to dive further into each stage of the power amp design, and to see the effects of the pHEMT switch by simulating the S-parameters at high and low band.


For more information on Plextek RFI, go to here.


See more tutorials by Plextek RFI here.



If you are interested in learning more about 5G design using ADS, an upcoming webcast will cover the “Circuit Design Phase” of a 5G system done all in ADS.

Click here to watch the webcast.


apply for free trial

Apply for a free trial of ADS.

This Case Study highlights work published in a recent paper in IEEE Power Electronics Magazine entitled Utilizing Modern Design Methodologies for Wide-Bandgap Power Electronics by my colleague here at Keysight EEsof EDA, Chris Mueth, and by Rakesh K. Lal of Transphorm, Inc. The high di/dt and dV/dt edges in switched-mode power supplies (SMPSs) combined with layout parasitics can create unwanted voltage spikes. The authors demonstrate that EM-circuit co-simulation can predict these effects. With the insights from this predictive tool in hand, they rapidly explore the design space and mitigate the impairment. The time and money spent on board spins is reduced and the time to market improved.

The Challenge

Since GaN switches are intrinsically very fast, one can have a very high change in voltage versus a given change in time (dv/dt) (>300 V/ns) and a change in current versus a given change in time (di/dt) (>5 A/ns). So, designers need to use good design practice for high-frequency layouts. Three cardinal rules that apply are:

  • Minimize capacitances to ground or other nodes at high dv/dt nodes to minimize Ispike = C dV/dt
  • Minimize parasitic inductance in high di/dt branches to minimize Vspike = L di/dt
  • Guard or shield high-impedance signal nodes, such as the gate of a drive transistor with appropriate guard rings and shields.

Physical prototypes are costly and time consuming to build and don't give insight into details like current crowding (which is indicative of excess inductance). But virtual prototyping in a tool like ADS (which allows EM circuit co-simulation) do exactly this. 


The Solution

The authors used ADS to gain insight into design weaknesses. The key point here is that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along with the effects of the layout. You can plot the voltage spikes and do "what if..." design space exploration, such as using a ground plane for the return current, to minimize their effects.


The Results


The Transphorm reference design analysis used the Momentum method of moments EM field solver. The EM-model extraction took roughly one hour. The tool automatically creates the components representing the layout from the port-to-port network parameters generated by the EM field solver. The analysis tool then simulated the circuit schematic including the extracted model in the time domain.


After experimenting with various "virtual prototypes", the final reference design utilized two power planes, which were poured onto two different PCB layers. This provided the best possible reduction in power plane inductive parasitics. In addition, the power planes were placed close together and provided an additional capacitance benefit. As a best practice, the ground layer was located under the main trace routing layer to provide additional capacitance to help reduce the stray inductance of these traces. 


The reference design produced an efficiency of 98.5% for the buck half-bridge configuration. This correlates well with the 98.3% efficiency seen in the simulation. The gate-driver waveforms also correlated well.


Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!


Best regards,

-- Colin


PS Here's the link to request an ADS evaluation license if you want to try it.

The trend in switched-mode power supplies is to use wide band gap devices because these enable a higher switching frequency and higher edge speeds (the “di/dt” of the switched loop). These two in turn enable a smaller, lighter, cheaper power supply because the energy storage capacitors and magnetics can be smaller if you top them off more frequently. The higher edge speeds enable higher efficiency because there’s less heat dissipated when you have lower switching losses because the transistors spend less time in the dissipative cross over region.


These high slew rates come with a dark side, in particular the large spike voltage and noise generated by the layout parasitics, particularly inductance, of the PCB layout traces. This phenomenon is often called conductive electromagnetic interference (conducted EMI).


My colleague, Andy Howard, talked about how to deal with this a while back in his video entitled “How to Design DC-to-DC Power Converters”, but a frequently asked question was “When should I start to worry about layout parasitics inductance? Is there a quick rule of thumb that says kind of ‘Caution: Further investigation’s needed?’” The answer is "Yes!" and this follow up video is about how to make these estimates. Here's the link:


How to Estimate Voltage Spikes from Layout Parasitic Inductance in Switched-Mode Power Supplies


Layout parasitics cause spike voltages in the switched loop of a switched-mode power supply

Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.


This week we are taking a break from Signal Integrity. In this post, I will “demystify ultra-low impedance measurement.”



To measure ultra-low DC resistance, instead of using a traditional 2-terminal sensing, one uses 4-terminal Kelvin sensing to avoid contact resistance. Similarly, instead of using the 1-port method to measure low impedance of the Power Distribution Network (PDN), we use the 2-port shunt technique, shown in Fig. 1.


Fig. 1: 2-port technique for ultra-low impedance measurement.


In the following paragraphs, I will show you that not only does the 2-port technique give us more measurable signal levels, it also helps us reduce the effect of contact resistance. 


Why Use the 2-port Technique?

In the March 2010 issue of the PCB Design Magazine, Mr. Istvan Novak pointed out “S11 VNA Measurements Don’t Work for PDN Measurements.


It is true. If I assume the device under test, the PDN, has 10 mOhm impedance and port impedance is 50 Ohm, the S11 calculation,




gives me -0.003 dB, which is easily masked by noise or bad calibration.  


Even if I have an ideal VNA with no noise and with perfect calibration, the contact resistance from the test fixture to the device under test, typically in mOhm range, is large enough to influence the result of the measurement significantly.


Fig. 2: Illustration of contact resistance in series with impedance under test.


To tell how contact resistance impacts the impedance calculation, I need to derive the extracted impedance in terms of measured S11. Using the schematic shown in Fig. 2, I would write



According to the impedance extraction equation, the contact resistance is directly influencing the extracted impedance. Worse yet, since the impedance and the contact resistance are of the same order of magnitude, I know the impedance extraction result is highly sensitive to the contact resistance.     


2-port Ultra-low Impedance Measurement Technique  

Shown in Fig. 3, the 2-port ultra-low impedance technique connects the device under test in shunt with the ports and uses S21 to extract the impedance under test.

Fig. 3: Ultra-low impedance measurement uses S21 to measure and extract the impedance under test.


Note that because S21 is the response of port 2 by the excitation from port 1, it’s analogous to using port 1 as a current source and port 2 as a voltage probe in DC 4-terminal sensing.     


Applying S-parameter analysis to the circuit in Fig. 3, the S21 of the device under test is: 



Putting in the numbers (Zport = 50 Ohm, ZDUT = 10 mOhm),



Given a good VNA, I should be able to measure down to -68 dB.


As shown, the 2-port technique is more suitable for ultra-low impedance measurement. The measured S21 is in the -60 to -80 dB range, more approachable than the S11 in milli-dB range.


So far, I have shown S21 produces more measurable signal levels than the S11 measurement. Next, I will demonstrate another great feature of 2-port measurement: insensitivity to contact resistance.   


2-port Technique Reduces Impact of Contact Resistance

Using the previous result, I continue and solve for the ideal extracted impedance given measured S21,



As shown, if there were no contact resistance, above calculation with measured S21 gives exactly the impedance under test. Let’s see what happens when I put the contact resistance back in the setup.


Fig. 4: Illustration of 2-port low impedance measurement setup with contact resistance.


Found in Fig. 4 is the 2-port measurement setup with contact resistance included. With the contact resistance, the extracted impedance is no longer just the device under test. The result of the impedance extraction is





Now, knowing both the contact resistance and the impedance of the device under test are in the mOhm range, I know the resistance error constant, Kr, is dominated by the sum of the contact resistance:


In addition, if I am measuring a low impedance PDN, S21 is going to be a number much smaller than 1, that is,



Given the approximations, I can rewrite the 2-port extracted impedance,




Great news! Since both S21 and the contact resistance are small numbers, the product is going to be even smaller! Consequently, as long as I am measuring low impedance, where S21 is a small value, the 2-port measurement technique is NOT sensitive to the contact resistance.  


Ultra-low Impedance Measurement Demystified  

Having derived the impedance extraction equations for both 1-port and 2-port measurements, I have demonstrated that the 2-port technique is a wonderful method to measure ultra-low impedance.


The 2-port low-impedance technique can examine more than just PDN. Because of the ability to measure ultra-low impedance, the technique is also useful to investigate the skin-depth of copper traces and a capacitor’s equivalent series resistance and equivalent inductance.    


That's this week's Tim's Blackboard. See you in two weeks!


To download ADS to create a virtual ultra-low impedance 2-port measurement test bench:

Further Reading

Ultra-Low Impedance Measurements Using 2-Port Measurements

Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.


This week on Tim’s Blackboard is “Your Channel, PRBS and the Eye.”



Previously on Tim’s Blackboard, we showed the convolution process and the helpful single pulse response. This week, we will extend the previously learned single pulse response (SPR) to explore Pseudo-Random Bit Sequence (PRBS) and the eye diagram, see Fig. 1.


Fig. 1: Left: A Pseudo-Random Bit Sequence. Right: An Eye Diagram.


What the Single Pulse Is Not Telling Us

Although the single pulse response gives us information on how a single pulse reacts to the channel under test, it does not tell us how previous pulses affect the shape of the current pulse.


In an ideal world, where the channel does not distort the signal with its frequency-dependent loss, the shape of each pulse is not dependent on other pulses. However, since we live in the real world, we often observe Inter-Symbol Interference (ISI) caused by rise time degradation, a consequence of frequency-dependent loss.  


Shown in Fig. 2 is the ADS simulation result of two different patterns followed by a single pulse pattern: 01000. After going through a channel with considerable frequency-dependent loss, the single pulse waveform comes after a string of one’s is not the same as the single pulse waveform comes after a string of zero’s. Because the previous symbols-string of one's-is interfering with the single pulse pattern, the voltage that is representing zero increased from 0 V to almost 0.3 V. If we are not careful, this increase would cause false triggering in the receiver. 


Fig. 2: Shown in ADS, the shape of the single pulse depends on the pattern before the pulse.


To add, although the single pulse response is helpful, it is rare for one to transmit or receive only a single pulse in practical high speed digital applications. Normally, the data pattern consists of different combinations of one’s and zero’s that we do not know a priori.


To mimic different data patterns and to characterize the level of ISI introduced by the channel, the Pseudo-Random Bit Sequence was born.


PRBS Pattern and the Channel

Shown in Fig. 3 is an example of PRBS. As the name suggests, the Pseudo-Random Bit Sequence is a sequence of one’s and zero’s that are independent of each other. The randomness provided by PRBS gives us some ideas on how the channel affects transmitted digital data.


Fig. 3: Example of a PRBS pattern at the transmitter side before going through the channel.


Much like the single pulse response, the response of the channel to PRBS is the convolution of the PRBS pattern and the impulse response of the channel.


From the single pulse response, we learned that after going through the channel, the sharp zero-to-one transition of a single pulse becomes a slower rising curve at the beginning. Also, the single pulse gains a longer tail (all thanks to frequency-dependent loss, which we will discuss in the future). In the same way, we should expect the received PRBS pattern to not have a sharp transition between the zero’s and one’s.


Fig. 4: After going through the channel, the sharp transition edges of the original PRBS pattern become slower rising and falling curves.


Fig. 4 shows the PRBS pattern after going through the channel. As expected, after going through the channel, the sharp transition between zero’s and one’s are reduced by the channel impulse response.


Eye Diagram: The Comprehensive Version of PRBS

Although PRBS gives us an idea on how the channel affects digital data pattern, the information is scattered throughout a large time scale. It is hard to come up with a figure of merit to describe the quality of the channel by looking at data that goes on and on in time. 


To create a better representation of the channel, we can manipulate the received PRBS waveform using our knowledge of the data coming in.


For example, if we are sending data at 10 Gbps, we know the unit interval (UI) of each bit is 0.1 nsec. Using our knowledge of the UI, we can “slice” the long received PRBS waveform and examine the waveform one UI at a time. Now, because we are also interested in the transition from one bit to another, we increase our observation window to 2 UI’s, corresponding to half of an UI before and half an UI after the current bit.


Fig. 5: Three example time slices of a received PRBS waveform. The data rate is 10 Gbps, corresponding to 0.1 nsec UI. To observe the bit transitions, the observation window is extended to 0.2 nsec. 


Shown in Fig. 5 are example “slices” of the received PRBS waveform. The eye diagram, which is the comprehensive version of the received PRBS waveform, is constructed by overlaying these observed partial waveforms on top of each other, as demonstrated in Fig. 6.


Fig. 6: Illustration of overlaying the three slices of PRBS waveform shown in Fig. 5 to create an eye diagram.


By combining many of these time slices, an eye diagram is formed. The resulting eye diagram for the example channel is shown in Fig. 7. According to the eye diagram, one would say the example channel is a good one because of the clear eye opening. With a clear eye opening, the receiver is able to distinguish the two different voltage levels at 100 psec.   


Fig. 7: The eye diagram result of the channel shows an open eye. The receiver can easily tell the high voltage level from low voltage level if a decision is made at 100 psec.


To further specify the quality of the channel, one can now quote the vertical amplitude measurements of an eye (eye height, eye level, etc.) and/or the horizontal timing measurement of an eye such as jitter or eye width.


How to Deal with a Closed Eye?

Although the example gives us a pretty clean and open eye, it is unlikely to always find such a pristine channel in practice. You are more likely to find a channel with an eye that looks like the one shown in Fig. 8.


Fig. 8: A channel that has an almost closed eye.


To deal with a closed eye, we will need to first find the root cause for the eye closure. We will do that in the next post!

That's this week's Tim's Blackboard. See you in two weeks!


To download a free trial of ADS to generate a PRBS pattern and an eye diagram:

Working with data tables is a basic skill every engineer learns early on in their career. When organized properly, tables can summarize a great deal of device data into a helpful information format, and that makes them extremely useful. A 1-page data table can pack as much punch as a thirty-page report that’s full of curves. The table significantly minimizes the time it takes engineers to find the information they're after, while also minimizing paper waste and saving trees!


But not every engineer wants their information displayed in the same tabular format. How the tables are created, organized and filled may differ from one engineer or application to another and that’s why the ability to customize tables is so critical. Doing so, allows engineers to derive the specific information that is so critical to optimizing their design. Unfortunately, generating tables and customizing them to meet specific needs is not always a straightforward task. And that can translate into wasted design time, added cost and slower time to market.


For those engineers wanting to quickly and easily customize tables, the answer comes in the form of Keysight Technologies’ Model Quality Assurance (MQA) solution. MQA is a well known, automated SPICE model validation software that allows engineers to check and analyze SPICE model libraries, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. MQA 2017 extends these capabilities by introducing the Python Report Formatting System (PyRFS) module, which allows engineers to customize tables—either generate new tables or update existing tables—in .csv and .xlsx file formats.


PyRFS is simple enough to generate all sorts of tables quickly, with plenty of options to customize those tables in a flexible and scalable way. For engineers using MQA, that means the ability to sort, filter, formulate, format, and layout data in many different ways. It also enables them to query and have fine control over MQA project results.


And, because it’s Python based, engineers can even feel free to blend in their own favorite Python stuff. For you personally, having access to this functionality promises to cut your design time and speed time to market.


But, how do you leverage this module? To do that, I’ll walk you through a simple, yet complete flow for creating a .xlsx file using the table in Figure 1 as an example. The table filters and sorts W/L/T for certain device targets (Idsat).

excel example table for MQA module

Figure 1. Example table.

The example table comes from the QA result of one MQA rule “Model Scalability -> Check Idsat vs L,” where there are Idsat curves from 3 temperatures and different W and L. The demo project to reproduce this example can be found as $MQAHOME/kefrfs/python/demo/data/. The first few lines of the code for generating this table are shown in Figure 2.

python code for MQA module

Figure 2. Initial code for creating the table in Figure 1.


In Figure 2, line 1 and 2 import necessary Python modules; “os” is Python’s native module for the operation system, and “pyrfs” is the module that comes with MQA 2017. Line 4 gets the current python file’s directory, while line 5 locates the example MQA project folder’s path. Line 6 prepares the option called “config,” which specifies that the project’s path is to be fed into line 7. Line 7 then creates a data provider “dp”, and gives it access to all of the information of the specified project for you to query.


On line 9, the “dp.query()” function is called by specifying “rule_group,” “rule,” and “check” as arguments. The values of these arguments are the folder names, respectively. The “dp” object has been narrowed down to information only from this node. Lines 10 – 12 are designed to get W/L/T as conditions, while line 13 gets Idsat as a target.


Figure 3 shows the next few lines of code. On line 15, a “table” is created by calling “rfs.ReportTable()” and giving “example_idsat_table” as its name. At the end, a file with this name is created.

 additional lines of code for MQA module

Figure 3. Additional lines of code need to generate the table in Figure 1.


Line 16 defines a RightLayout and associates it with the “table.” A Layout is how we fill up the table. RightLayout means PyRFS will automatically fill the table from left to right, starting from the top-left cell “A1” by default, and growing rows and columns as necessary so that you don’t need to worry about cell indices.


Line 17 adds W, L into the table with a few options to make them appear in one column with a certain format, ascending, and filtered by L=Lmin. Line 24 adds Idsat into the table, and repeats it in 3 columns because it is dependent on the 3 temperatures to be added in line 25. Once these constraints are well defined, lines 30 and 31 fill up and save the table, respectively.


From this simple example, it’s easy to see how useful the PyRFS module is and how helpful it can be in automating your table generation tasks. For more information on the PyRFS module functionality and step-by-step examples of how it can be used, refer to the “PyRFS Function List” at the end of the blog and check out the online PyRFS Tutorial at:


PyRFS Function List

The MQA 2017 PyRFS is a powerful Python module for easy, yet fully customizable table generation and reporting. Below is a summary of the functions that PyRFS provides:

  • Automatic extraction of constraints (data collections) from MQA result directories
  • Generation of tables and ability to save them as Microsoft Excel .xlsx files or .csv files on Linux and Windows platforms
  • Support for updating .xlsx files under Windows.
  • Support for sorting and filtering per user specification
  • Support for customized formatting of constraints in tables
  • Support for formulas calculated from other constraints in tables
  • Ability to divide data into different tables, sheets, or files per user specified conditions


apply for a free MQA trial

FREE Evaluation of MQA | Keysight EEsof EDA  

The fundamental goal in cellular and network wireless development is maximizing antenna performance while minimizing antenna size. In order to achieve this, antennas have increased in the number of array elements and in complexity of broadband networks, requiring highly accurate simulation programs for significant designs and tests. With ADS 3D EM simulation software, users can easily design and simulate many different types of antennas. EMPro can simulate the antenna in realistic surroundings, including the phone components, housing and even the human hand and head. Compliance testing can also be performed, such as specific absorption ratio (SAR) and hearing aid compatibility (HAC). Below are two examples of types of antennas you can design and simulate with ADS. Visit Keysight’s EM Applications Page for more examples!


  1. Multi-Band Planar Array Antenna

    Large-array antennas become more challenging when the antenna is used for multiple bands. The field solver required to handle the capacity and speed is a design challenge for many engineers. One approach to this challenge is to divide the EM problem into small “sub-cells” that are integrated individually without carrying out an EM simulation at the full structure level. However, the coupling between the sub-cells will not be taken into account.

    Using Momentum 3D Planar EM Simulator, you can design and simulate an entire multi-band planar array antenna for communication and radar applications with optimum accuracy. The complexity of this design requires a highly accurate simulation software, such as Momentum, to accurately characterize the antenna in terms of radiation and return loss.

    Figure 1: Using Momentum 3D Planar EM Simulator, you can design and simulate an entire multi-band planar array antenna for communication and radar applications.

  2. 8x16 Patch Array Antenna
    In order to create the desired directive radiation patterns, designers arrange multiple antennas so that their coexisting wave patterns add constructively or destructively in a specific formation. The main lobe antenna can be steered by changing the phase of excitations at each array element. Depending on the number of array elements and the complexity of the feeder network, the simulation of a patch array antenna can be quite challenging. Although simulation time and speed are mostly related to the problem size, another effect on simulation time is the frequency bandwidth.
    The EMPro FDTD simulation engine is preferred because it produces a wide band simulation result with a single simulation. No frequency sweeping is necessary. FDTD also uses less memory while speeding up the simulation utilizing GPU acceleration.

    patch array
    Figure 2: The EMPro FDTD simulation engine is preferred because it produces a wide band simulation result with a single simulation. No frequency sweeping is necessary.




These are two of many prevalent applications of ADS and EMPro that can be found on Keysight’s EM Applications Page. Apply for a free trial of EMPro today!

Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.


This week on Tim’s Blackboard, convolution workspace!

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