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Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.

 

This week on Tim’s Blackboard is “Root Cause of Eye Closure,” where we study one of the root causes of eye closure.

After reading the post, download the attached ADS workspace to experiment with Fourier Transform and channel simulator!

 

Introduction

Even when you do everything right, i.e., using controlled impedance lines and termination strategy, loss remains a problem when traces are long and when transmitting in the Gigabit regime.

 

Specifically, it is the frequency-dependent loss that significantly degrades the signal quality at the receiver. Fig. 1 demonstrates the resulting eye diagrams of frequency-dependent loss and constant loss with the same loss at Nyquist frequency.

Fig. 1: ADS simulation of two different channels with the same loss at Nyquist frequency. The eye closure of the channel with frequency-dependent loss is more prominent than the channel with constant loss (Eye Diagrams are offset to illustrate the eye closure).

 

Given the same transmitter, receiver and same loss at the Nyquist frequency, the channel with frequency-dependent loss introduces more Inter-Symbol Interference (ISI) and degrades the eye horizontally more than the channel with constant loss.

But how?

In this post, we will transmit a single pulse and use our knowledge of time domain and frequency domain transformation to learn the impact of frequency-dependent loss.

 

Single Pulse in Frequency Domain

To view the pulse in frequency domain, we perform Fourier Transform to decompose the input signal, channel, and output signal into their corresponding frequency spectrum. Fig. 2 shows the mathematical relationship of the input, the channel, and the output.

 

Fig. 2: Illustration of performing Fourier Transform on the time domain input-channel-output relationship.  

 

After the transformation, the time domain convolution corresponds to multiplication in the frequency domain. The output spectrum is the product of the input spectrum and the channel frequency response after multiplication.

 

Fig. 3 demonstrates a single pulse going through a channel in both time and frequency domain. Since the frequency domain and time domain are two sides of the same coin, if we have the frequency spectrum of a time domain signal, we could apply Inverse Fourier Transform on the spectrum to retrieve the time domain representation.

 

Fig. 3: Sending a single pulse through a channel.

 

We see difference in the shapes of the input and output single pulse spectrum in Fig. 3, and we know the channel ought to change the input spectrum, but

How does the channel frequency response cause the spread of the output time domain waveform?    

To answer the question, let’s take a closer look at the time and frequency domain relationship.

 

Reconstruction of Waveform from Spectrum

Frequency domain representation shows how different frequency components interact with each other to create the time domain waveform. The constructive and destructive interference of sine waves of different frequencies works together to form the time domain waveform.

 

Thus, the shape of the frequency spectrum is important when one wants to reconstruct and maintain the shape of the original time domain waveform. For example, if we were to divide the the amplitude of the entire spectrum by two, we should expect the resulting time domain waveform to still be a single pulse, but with half of the original amplitude.

Fig. 4: Time domain and frequency domain representation of the original and modified waveforms in ADS. Because different frequency components work together to produce the shape of the original pulse, if the relative strengths of all components are identical, the shape of the time domain waveform is the same

 

Fig. 4 shows a modified spectrum of the same shape and the result of Inverse Fourier Transform. As we expect, because the same modification, dividing by two, is done to the entire spectrum, the relationship between different frequencies is the same. Consequently, the shape of the single pulse waveform is maintained in the time domain, and the peak amplitude is indeed half of the original.

 

However, if we don’t treat the spectrum as a whole, and we alter only a small part of the spectrum, we expect to see a small change in the spectrum to produce a dramatic change in the shape of single pulse waveform, as shown in Fig. 5.

 

Fig. 5: Although the spectrum is modified a little bit, the relative strengths of different components are different. The new shape of the spectrum no longer corresponds to the original single pulse.

 

Although Fig. 5 is an extreme case where a small part of spectrum is removed, it underscores the importance of treating a given spectrum in its entirety to maintain the corresponding time domain waveform.

 

To see how the single pulse would look after going through the channel, let’s take a look at how the channel treats different frequency components.  

 

Channel Frequency Response Changes Spectrum

We can see from Fig. 6 the frequency response of the channel modifies the spectrum differently at different frequencies. Therefore, we expect the shape of the reconstructed pulse to be different from the original.

Fig. 6: Channel frequency response shows more attenuation at higher frequencies than lower frequencies.

 

Specifically, because the channel attenuates higher frequency components that make up the sharp transition more than the lower frequency ones, at the output of the channel, the rising and falling transitions of the pulse will spread. 

 

A comparison of lossy channel and lossless channel in Fig. 7 shows consistent result with our expectation. The lossy channel distorts the spectrum of the original input pulse unevenly. Seen in the time domain, the sharp transitions of the original pulse spread out at the beginning and the end.

 

Fig. 7: Because the lossy channel attenuates higher frequency components more than lower frequency ones, the sharp transitions at the beginning and the end of the single pulse spread out.

 

The spreading of the single pulse is known as the inter-symbol interference (ISI) because the current pulse interferes with the one pulse before and the one after. To reduce ISI is to reduce eye closure.      

 

How to Avoid Eye Closure

Because of frequency-dependent loss closes the eye, to open the eye, we do the following:

  1. Reduce the amount of loss,
  2. Remove the frequency dependence of the loss.

 

Given a fixed data rate, to reduce the amount of loss, we can:

  • Keep trace as short as possible,
  •  Use substrate with lower Dk and Df,
  • Use smoother conductor and as low resistance as budget allows.

 

To remove frequency dependence of the loss, we can equalize the spectrum with different equalization techniques:

  • CTLE: Continuous Time Linear Equalizer,
  • FFE: Feed-Forward Equalizer,
  • DFE: Decision Feedback Equalizer.

 

Fig. 8 shows an example of applying equalization to open an eye.

 

Fig. 8: Equalization result of ADS channel simulation (Eye diagrams are offset to illustrate the opening).

   

The next blog talks more about the different equalization techniques and how to perform them in ADS.

Make sure you apply for a free trial and download the attached workspace to experiment with Fourier Transform and channel simulator!

 

That's this week's Tim's Blackboard. See you next time!

Signal and Power Integrity engineers look to ADS for the correct treatment of high-speed effects like distortion, mismatch, and cross-talk. Building on the strong foundation and loyal users ADS has amassed through the years, ADS 2017 delivers new options and functionality that enable it to be the tool today's designers need to get ahead.

 

The latest release of ADS is a stronger, faster, and more comprehensive platform for signal and power integrity analysis. Read about the top 10 new features in ADS 2017 for Signal and Power Integrity Engineers or watch the video.


 

10. Improved substrate editor

The new and improved substrate editor has an efficient edit feature for a larger number of layers. The simplified editor interface reduces simulation setup time and increases productivity.

ads2017 substrate editor

9. Fast Wire labeling

Labeling ports with the correct node names is time consuming, especially when you have many ports. With the new CSV import labeling, naming more than 10 ports is simple. 

ads2017 fast wire labeling

 

8. Parallel Sweep on windows

In ADS 2017, Batch simulation is able to run in Turbo mode in both Linux and windows. Using the 8-pack Element license and simulation manager, you can unleash the parallel computing power of your workstation PC. Reduce simulation time of large sweeps with simulation manager.

ads2017 parallel sweep

 

7. Statistical mode PAM -4

To simulate a PAM-4 signal down to 10 ^ -16 BER, a bit-by-bit simulation would take hours. ADS 2017 now supports PAM-4 in statistical mode. You can directly simulate PAM-4 to very low BER in a matter of seconds to minutes.

 

6. Mixed-mode S-parameter Checker

In the improved S-parameter checker, you can now convert single-ended S-parameters to mixed-mode in a few clicks. Save time and increase your productivity by letting the S-parameter checker show you the mixed-mode response.

ads2017 mixed mode s-param checker

 

5. S-parameter Spectral Thresholding

Usually, you would expect simulation speed to decrease with higher port count. In ADS 2017, the spectral thresholding algorithm removes weakly coupled ports before simulation. The result is faster simulation speed for a higher port count, without sacrificing accuracy.

ads2017 faster simulation

 

4. New and improved IBIS Components

Are you looking for specific pins in your IBIS model to interact with? The improved IBIS component interface helps you quickly sort and select desired pins. With built-in smart default settings, the IBIS schematic is cleaner, and setup time is faster.
ibis components

 

3. 3D Via Designer: Enabling Access to Accurate Via Models

A crucial problem when simulating high-speed signal interconnects is a lack of access to via models that are accurate at high frequencies. To solve this problem, ADS 2017 introduces Via Designer, a tool for creating and modeling PCB vias (single-ended or differential), while giving you full control over the via specifics.
ads2017 3d via designer

 

2. PIPro Bill of Materials Optimization for Decaps

Decap Optimization in PIPro can take all the decaps as laid out on the board, and search for the optimal solution that meets the desired target impedance profile. The user can define an optimal solution, by specifying weighted criteria such as: number of decaps, unique models, vendors, or cost. PIPro's algorithm intelligently ranks your best candidate solutions so you arrive at the best trade-off between performance and cost.

decap output

 

1. PIPro DC Electro-Thermal Capability

To find the true IR-drop of your power distribution network, thermal effects need to be considered in your analysis. PIPro performs an automated, iterative electric and thermal solve on each PDN, providing thermal insights to every power integrity engineer. PIPro calculates the temperature distribution of the board, so you can ensure the temperatures of vias, traces, and devices in your design are within the specification.  

ads2017 electro-thermal

 

 

These 10 new features are just the beginning of all the new capabilities and usability enhancements in the latest release of Advanced Design System (ADS) 2017. Along with improvements for the Signal and Power Integrity Designers are improvements for RF/MW designers doing RF front-end module and Silicon RFIC design. Check out all the new features on the web page and apply for your free trial of ADS 2017 today.

free trial of ADS 2017

FREE Evaluation of ADS | Keysight EEsof EDA  

Many of you know Matt Ozalas, RF Design Engineer at Keysight Technologies, and his infamous YouTube video series, How to Design an RF Power Amplifier. I got a chance to talk to him about what he’s most excited about in the latest ADS release.

Matt Ozalas, RF Design Engineer at Keysight Technologies

 

Kaelly: I heard ADS 2017 is being called the “3D release”. What 3D capabilities are you excited for?

 

Matt: It’s 2017, we’ve got hoverboards and self-driving cars -- we should be designing in 3D by now, right?  Besides the “wow” factor, some tasks are really useful to do in 3D.  I think a lot of designers will feel the same way after trying the new capabilities in ADS 2017 out.  In ADS 2017, those 3D capabilities span design, simulation, and visualization.   So, physical design becomes more realistic early on, the simulation is easier to set up, the results are more accurate, and the analysis becomes more meaningful. 

 3D layout, ADS 2017

In ADS 2017, you can design a layout in three dimensions. You can route a trace or stitch a VIA more precisely in a dense module or chip, and you can select complex structures much more easily in 3D.  This might seem trivial but we’ve all been in that spot where a VIA gets missed or the routing goes to the wrong layer and that causes big problems down the line. Designing in 3D prevents these mistakes from the outset.  The 3D selection also helps if you’re trying to do an EM simulation, getting all the right structures selected is not always easy.  You can even thermally simulate multiple technologies at the same time, like a chip stacked on a substrate.  Let’s face it, no one can afford to overlook these things in the design process anymore, mistakes cost too much and reliability problems are too critical to leave to chance.  Just ask those people making hoverboards.

 RFIC layout, ADS 2017

Kaelly: Designers are always looking for ways to save time. Is ADS 2017 faster than its previous release?

 

Matt: Yes, let’s look at EM simulation for example.  The Momentum 3D planar EM simulator now uses multi-threading for substrate calculations in ADS 2017.  What does that mean?  Well, typically substrate calculations only use one processor, but for example, your Windows machine probably has four processors.   In ADS 2017, Momentum farms those calculations out to the different processors and so on that Windows machine, you will see a 4x speed improvement in the substrate calculation.   By the way, in Momentum, the substrate calculation is usually the most time-consuming piece.  Now, what about 3D Finite Element Method (FEM) Simulation?  Well, in ADS 2017, this 3D engine has a turbo mode which distributes the simulation frequencies to different processors, and that of course, speeds up the simulation time dramatically.   

 FEM in ADS 2017, finite element method

Kaelly: I know there are many usability improvements in ADS 2017. Which ones are most exciting to you?

 

Matt: The way I look at it, no matter how good a capability is, if it isn’t easy to use, I probably won’t use it.  So 3DEM simulation is faster, right?  Great, but what about getting your design into that EM engine?  If that takes too long, all the speed improvement is less meaningful.   In ADS 2017, we looked closely at the EM setup process, like what steps designers take before they run an EM simulation.  They set up a substrate, then perhaps if they want to analyze a sub design, they’ll cut that part out, remove unwanted metal, add ports, go play around with some EM settings, and finally click run.   A lot of steps. 

3D EM in ADS 2017

 

In ADS 2017, you will find that every one of those steps is easier.  The substrate editor has a table definition feature which enables you to easily create and modify highly complicated substrates with lots of layers.  A grouping capability allows you to much more easily group items you want to be modeled. There are even features that allow you to more easily place multiple ports and pins, and assemble and define ports. Separately, these features might not seem all that exciting, but put them together and the result is undeniable: fast and simple EM simulation setup.

 

Anyone who has ever used the ADS Electro-Thermal simulator knows that defining a substrate involves a text-based file, but not anymore. With ADS 2017, you can accomplish that task using the substrate editor. Just imagine how much easier it will be to visualize your thermal stackup using the substrate editor, rather than writing it into a cryptic text file.

 

Another great new feature in ADS 2017 is its multi-technology support (e.g., Chip on Package). In the past, if you had a chip that went into a board or module, you then had to simulate those two technologies. You could do it, for sure, with the ADS Electro-Thermal simulator, but it required a 3-page procedure and was impossibly difficult. With ADS 2017, that simulation of multiple technologies just works.

 

Kaelly: What’s the ADS Python Data Link that I keep hearing about?

 

Matt: I have been using this capability for all kinds of neat things. This is what I’m most excited about in ADS 2017. In essence, you can take your ADS simulation result and run it through a Python script by just using an equation in data display. The ADS data goes into Python, the script gets run, and the results come back to ADS in one step.  It’s like hooking a rocket engine onto ADS Data Display – and the best part is you never have to leave the simulation environment.  The possibilities are endless: 3D plotting, instrument connectivity, loadpull contours from measured data, all that stuff becomes easy to do, and you don’t even need to know Python to take advantage of it because the scripts already exist and they just run in the background.  The best application I’ve seen of this feature so far is plotting ADS simulation data on a cylindrical 3D Smith Chart, called the “Smith Tube”.  Look up the Smith Tube on IEEE Explore, it is so cool.  It will change the way you think about circuit design – seriously!

 ADS 2017 Data Link with Python

Kaelly: Thanks Matt! I’ll have to check that out.

 

If you want specific information on any of the features Matt mentions, and some that he didn’t, check out the ADS 2017 release webpage.

 

free trial of ADS 2017

FREE Evaluation of ADS | Keysight EEsof EDA  

LTspice

 

LTspice is a freeware SPICE simulator offered by Linear Technologies (now a division of Analog Devices Inc.). LTspice was originally called “SwitcherCAD” and was designed with switch-mode power supplies in mind. As a result, it is widely used in power electronics. IC-CAP may be used to generate device models based on measured data using multiple simulators: not only our own ADS Transient and Harmonic Balance (for periodic state state) simulators, but also transient analysis in LTspice, giving engineers the option to create workflows as needed.  For an engineer that might want to generate a model based on measured data using LTspice as the simulation engine, here's a look at how you do that.

Flow diagram, showing LTspice to IC-CAP link

 

But before delving into the details of that process, it's worth noting that as of this writing, the LTspice documentation describes support for seven different MOSFET device models:

 

LevelModel
1Shichman-Hodges
2MOS2 (A. Vladimirescu and S. Liu, October 1980)
3MOS3, a semi-empirical model
4BSIM (B. J. Sheu, D. L. Scharfetter, and P. K. Ko, May 1985)
5BSIM2 (Min-Chie Jeng, October 1990)
6MOS6 (T. Sakurai and A. R. Newton, March 1990)
8BSIM3v3.3.0 from University of California, Berkeley, July 29, 2005
9BSIMSOI3.2 (Silicon on insulator) from the BSIM Research Group, February 2004.
12EKV 2.6 (M. Bucher, C. Lallement, F. Theodoloz, C. Enz, F. Krummenacher, June 1997.)
14BSIM4.6.1 from the BSIM Research Group, May 18, 2007.
73HiSIMHV version 1.2 from the Hiroshima University and STARC.

How to Link IC-CAP to LTspice

If you have no background on how to link IC-CAP to an external simulator, I recommend you read my previous post
entitled, “Link the IC-CAP Modeling Tool to External Simulators.” It will provide you with an overview of the basic process, along with some troubleshooting tips.

 

LTspice is not officially supported by IC-CAP. However, we have a workaround to successfully link IC-CAP to LTspice IV by disguising it as a SPICE3 look-alike. To date, this workaround has not yet been tried on LTspice XVII.

 

Assuming you have LTspice installed on your system, here are the steps:

  1. Append the following line into your $ICCAP_ROOT/iccap/lib/usersimulators file.

    ltspice spice3 $ICCAP_ROOT\src\ltspice3.bat "" CANNOT_PIPE

    We used spice3 as the template_name, so that IC-CAP will treat the simulation input/output files as if it were for SPICE3, which is natively supported.

  2. Download the ltspice3.bat file from the attachment below.

    Note, the file was renamed to ltspice3.txt for security concerns. After you download it, please rename it back to ltspice3.bat.

    Open and edit ltspice3.bat on line 30. Make sure it reflects the correct path to the LTSpice IV executable scad3.exe, as shown below:

  3. Move the ltspice3.bat file to directory $ICCAP_ROOT/src.

  4. Restart IC-CAP.

Verify the Simulation Link to LTspice IV

 

Now, let’s verify that it works, to ensure we can indeed use LTspice as the simulator engine for IC-CAP model parameter extraction. To do that:

  1. Load the following *.mdl example file from within the IC-CAP program:../Examples/model_files/mosfet/nmos3.mdl
  2. In the model Variables, add the variable SIMULATOR and set it to ltspice.

    Image

  3. Go to the /large/idvg/ setup, and clear out the simulated data using Clear -> Simulated. Any previously saved simulation will be gone.

    Image

    We now see only the measured data (symbols) on the plot, whereas simulation data would be shown as solid:
  4. Simulate.

    Image

  5. In the same DUT/Setup, open the plot tab under the /large/idvg/idvsvg plot, and confirm that the simulated data appears.

    Image

The simulated data is represented by solid lines on the plot.

 

So there you have it! By following this process, you can now use LTspice as your simulator for model parameter extraction within IC-CAP.

A new video by Wolfspeed demonstrates how the Wolfspeed ADS process design kit (PDK) is configured to work with the Keysight ADS electrothermal simulator to co-simulate electrical and thermal performance together.

 

Figure 1. Wolfspeed’s process design kits work with Keysight Technologies’ ADS electrothermal simulator to co-simulate electrical and thermal performance together.

 

The electro-thermal simulation capability allows designers can see the impact of thermal effects on circuits while still in the design stage, and account for those effects early on in the design process. This becomes especially helpful when using a high power density technology like SiC or GaN.

 

Wolfspeed is the largest SiC and GaN wide bandgap Power and RF fabrication facility worldwide. They are the leading supplier of SiC and GaN materials, providing lighter, faster, and more powerful devices to industry experts around the world. Wolfspeed offers non-linear, scalable GaN HEMT models for MMICs, as well as full PDKs for Keysight Technologies’ Advanced Design System (ADS).

 

 

Figure 2. Wolfspeed’s video shows allows designers can see the impact of thermal effects on circuits while still in the design stage, and account for those effects early on in the design process.

 

Because of their dedication to a more energy efficient future, Wolfspeed takes the lead in the innovation of power and wireless systems with wide-band semiconductors. These materials enable devices to function at higher voltages, frequencies, and temperatures, allowing for broader use of alternative energy devices. The electro-thermal simulator accounts for significant thermal effects that often occur with these increasingly popular materials.

You can watch Wolfspeed’s new video below. They walk you through the process of co-simulating electrical and thermal performance using the Wolfspeed PDK.

 

 

To learn more about the ADS Electro-Thermal Simulation Element, watch this 30-second video or visit http://www.keysight.com/find/eesof-ads.

 

 

FREE Evaluation of ADS | Keysight EEsof EDA 

Keysight’s latest release of SystemVue 2017 is the industry’s leading simulation platform for system design and verification, giving designers the earliest possible head start in entering the high-margin 5G market.

 

With its unique 5G functionality, SystemVue 2017 now makes it possible for 5G cellular system, RF component, and chipset vendors to create pre-5G-compliant reference designs. Designers can start pre-5G now and continue forward into the final 5G New Radio (NR) standard as it becomes available.

 5G verification library

Figure 1. SystemVue 5G Verification library merges Verizon and KT 5G wireless standards with 100GHz mmWave channel model and adaptive beamforming needed for 5G cellular base stations and handsets.

 

The new software adds functionality not possible with other 5G electronic design automation (EDA) solutions on the market today. Unique features include the ability to incorporate S-parameters of off-the-shelf phase shifters and attenuators, and X- or Sys-parameters of nonlinear amplifiers and mixers.

 

In addition to its powerful 5G and phased-array functionalities, SystemVue 2017 offers three important updates designed to enable early electronic product designs with high margin and volume potential for emerging standards:

 

  1. New Automotive Radar library, which features unique pedestrian channel models with micro-Doppler detection of moving pedestrians
  2. NB-IoT or LTE-Advanced Pro, which is an enhancement to the LTE-Advanced baseband verification library for validating Narrow-Band Internet of Things (IoT) product designs
  3. 802.11ax enhancement has also been added to the WLAN baseband verification library for designing even higher speed WiFi networking

 Phased Array Architext

Figure 2. SystemVue 2017 Phase Array Architect allows accurate RF S-, X- and Sys-parameters of amplifiers, phase shifters, attenuators to be used in Phased Array Antenna system design.

 

5G communications systems architects can quickly iterate and validate their 5G designs, allowing developers to cross traditional Baseband and RF boundaries in order to innovate the physical layer of next-generation communications systems.

 

For more information on SystemVue 2017, go to http://www.keysight.com/find/eesof-systemvue2017.

 

 

 


Get your free trial today!

 

 

A high-quality device model captures device behavior across geometry (W/L), temperature (T), drive voltage (Vdd), among numerous other input conditions. How much time do we spend trying to achieve a good fit across all these axes? What if we could easily bring up graphs of all key device targets such Vth (Threshold Voltage), Idsat (Drive Current), GM (Transconductance), and their variations across these dimensions?  We could then monitor them in one place, and tune or optimize model parameters while observing the agreement between measured and modeled data.  With Keysight’s Model Builder Program (MBP) 2017, we can achieve this goal. In this note, we are going to go through a couple of examples to show how MBP Script makes it possible to monitor device targets across the entire matrix of input conditions.

 

First, let’s look at the Threshold Voltage (Vth) variation as we vary device width (W) and length (L) on 4 sides of the W/L matrix, as shown below. 

Figure 1. Four sides of the W/L matrix for evaluation of Vth variation

 

The 4 sides of W/L space define the boundaries of modeled device sizes provided by a given semiconductor technology. A customer may use a geometry outside of this space, but will then need to re-target the model parameters for this unusual device.

 

Vth is the key device parameter of any transistor device, be it BULK, SOI or FinFET.  It defines when a transistor transitions from off to on.  If the Vth has been well modeled along the 4 sides of the W/L space, then we have good confidence that the model will work over the entire W/L plane. Both short and narrow channel effects will be covered.

By placing Tasks in sequence, a user may define a real modeling flow to be executed automatically.  A “Task” is object to represent a step in a flow, and is represented by a blue icon in the flow panel, as shown below in figure 2.  With Tasks, a modeling engineer can group modeling building blocks to extract the next logical group of device parameters.  In MBP, we may create a new Task button, as shown below, called “Display_Vth_Scaling_4_sides.”  By  clicking on this button, we can define and display the related graphs.

 

Figure 2. Display Vth W/L scaling plots by Task button clicking

 

In figure 2, we plot Vth in a 2x2 layout, where each quadrant represents one side of the W and L scaling space.  The solid represents simulated data and the square represent measurements.  The MBP tool is now ready for model tuning or optimization.

 

To create this beautiful matrix of graphs, we need to create a new Task from MBP Script window and name it “Display_Vth_Scaling_4_sides,” as shown in figure 3.  In the newly created Task, in its Plot Select tab, click the “Add Plot” button to add these 4 plots.  We may populate the “Plot Name” using 2 of the predefined plot groups “vth_l_vbs” and “vth_w_vbs.” In the “filter define” field, we may filter the data based on desired input conditions, like “w=max(w)”.  The filter definition is highlighted in green for the first plot where vds=abs(min(vds)) && w=max(w). In other words, we filter the data for the absolute minimum Vds, and maximum W input conditions. 

 

 

Figure 3. Create a Task by grouping Vth W/L scaling plots

 

MBP provides the most commonly used device targets, including Vth, Gm, Idsat, Idlin, etc. as well as common plot templates like the scaling graphs over W, L, T and Vdd.

 

One powerful plot type shows how well the model has been fitted across input conditions like geometry.  This is called an “Error Data Grid” plot.  In figure 4, we present the RMS error of device targets Vth and Idsat in our 2-dimensional geometry plane. However, we can choose pairs of input conditions to study, for example:

  • W and L
  • W/L and T
  • W/L and VDD

 

Figure 4. RMS Error plots of Vth and Idsat across W/L plane.

 

When tuning model parameters, we can observe the RMS errors update on the fly. For example, slightly different model parameter settings lead to the following Error Data Grid plots:

Figure 5. another state of the RMS Error plot of Figure 4.

 

The numbers are color-coded for quick and easy reading.

 

In figure 6, we illustrate how to create these incredibly useful Error Data Grid plots. In MBP’s Script window, we choose our device target (Idsat), specify the X and Y axes as ‘w’ and ‘l’ below, coloring for various RMS error ranges, etc. We can even add more targets to our Error Data Grid plot.

 

Figure 6. ErrorDataGrid plot creation

 

These newly created plots can be integrated in the Flow as another Task button, as shown below:

Figure 7. Display RMS Error plots by Task button clicking

 

Every Task object has a few properties of which “button mode” is one.  When the task is in button mode, then when you click it, it executes just that code to do an action, like extracting a group of parameters.  When the task is not in button mode, clicking on it has no immediate effect.  Rather, it marks where the flow may resume. 

 

By monitoring a model’s performance (RMS error) across all input conditions, MBP provides a high-level view of the model in real time.  Our modeling engineer may enjoy the peace of mind that the device model has been done thoroughly and accurately.

 

Please see the attachment below.  We have attached an example project that includes:

  1. demo data files
  2. demo model files, initial version and final version.
  3. script file that defines the flow Tasks and ErrorDataGrid plots

 

For more details about how to customize device targets and plots and how to customize the flow, please refer to the MBP Script tutorial.  https://devicemodelingworks.net/mbpst

 

ShuangCai

MALong

You have a waveform that was generated in MATLAB. How do you use that waveform as the source for a circuit in Genesys?

 

Keysight’s RF/Microwave Synthesis and Simulation Software, Genesys understands MATLAB. The full-featured MATLAB script debugger in Genesys enables you to develop error-free, fully compatible equations for data processing, simulation, and analysis. Genesys equation pages use MATLAB, so it is very easy to generate MATLAB waveforms in Genesys. You can paste MATLAB code directly onto a Genesys equation page to create any waveform.

 

Figure 1. You can easily import a MATLAB waveform into Genesys, and use that waveform as a source for a circuit.

 

Genesys Understands MATLAB

Running the MATLAB code in the equations page allows you to see and verify the waveform. Here, the waveform is stored and plotted in a variable called “PulseTrain”. The user will run the Equations first, and then the variable will be used by the source in the Genesys design.

 

Figure 2. The waveform is stored and plotted in a variable called “PulseTrain.” (Click image to zoom.)

 

How to apply the waveform to a circuit

In order to apply the waveform to a circuit, use a Custom Voltage source which allows us to specify a variable, PulseTrain, for the V parameter.

 

Figure 3. The variable PulseTrain is available for the source to use in the Genesys design.

 

From here, all that’s needed is to set up the Transient simulation for the desired time step and stop time. Run the simulation, and see the results below.

 

 

 

Summary

To use a waveform developed in MATLAB:

  1. Paste the MATLAB code that creates the waveform into an Equation page in Genesys.
  2. Assign the variable containing the waveform to a Custom Voltage source on the schematic.
  3. Run a Transient simulation.
  4. View the results.

 

Check out the related application note here.

 

 

 

 

Click here for a free trial of Genesys.

Having trouble getting started with your next circuit design? Keysight EEsof EDA’s YouTube channel is filled with “How To” videos and examples to help you with your complex designs. In each video, Keysight engineers walk you through the steps while also covering the fundamentals of each topic. At the end of each video, you can download the workspace to help get you started on your own projects. These five videos are a must-see for anyone working with Keysight ADS.

 

1. How to Design an RF Power Amplifier: The Basics

This video shows how power amplifier circuits work. If you are new to high-frequency power amplifier circuit design, this is the place to start. If you are an experienced designer, this video provides unique insights into the fundamentals that you may not have seen before. There is also an entire playlist dedicated to this topic on our YouTube channel.

 

Questions answered include:

  • What is AC power?
  • How is AC power generated and dissipated?
  • What topologies are convenient to use for power amplifier circuits?
  • What is a loadline and how can this be used to design a power amplifier?

 

 

2. How to Design for Power Integrity: Selecting a VRM

This video is one of a three-part series in Power Integrity tutorials. There are many factors to consider when selecting a VRM (Voltage Regulator Module), and this video covers two: Output Impedance and PSRR (Power Supply Rejection Ratio). This video uses measurement-based simulations to show that current mode topology is the best choice for flat impedance VRM.

 

Questions answered include:

  • What factors should I consider when selecting a VRM?
  • Why is flat impedance the PDN design goal?
  • Why is VRM selection not arbitrary?

 

3. How to Use Fixture De-embedding to Match Signal Integrity Simulations to Measurements

This video provides a quick 4-step process to show how to de-embed a fixture from a measurement to validate a PCB channel model, and then how to embed the fixture with the model to do a direct compare of simulation to full-path measurement both in the frequency domain and time domain.

 

Questions answered include:

  • How can I match SI simulations to measurements?
  • How can S-parameters simplify the problem?
  • What is the best process to solve this problem?

 

4. How to Design Phased Array Systems

This video discusses the most important considerations for phased array system design, especially popular for 5G. It begins with the basics of phased array design, then covers 4 key parameters of phased array architecture. After watching this video, you will be able to download the simulation tool, SystemVue, to perform your own phased array modeling and simulations.

 

Questions answered include:

  • How does a phased array work?
  • What are the key elements of phased array architecture?
  • What factors influence the far field pattern?

 

 

 

5. How to Understand 5G: Beamforming

This video guides you through what kinds of multi-antenna system architectures are being researched for the next generation 5G standard. It provides examples with end-to-end link level simulation and demonstrates key technical issues of different multi-antenna beamforming system design under mmWave channel environments.

 

Questions answered include:

  • How does beamforming work?
  • How can I model and simulate for key multi-antenna systems architectures?
  • Is hybrid beamforming too good to be true?
  • What is the 3GPP channel model for mmWave frequency band?

 

 

 

These are just five of the growing library of “How to” videos from Keysight EEsof EDA. Apply for a free trial of ADS or SystemVue to get started on your own designs.

 

 

 

Click here to apply for a free trial of ADS.

 

Keysight EEsof EDA is introducing a new set of tools for 5G, starting with pre-5G modulation analysis. This new technology is geared toward innovators with 5G testing in mind.  The 89600 VSA software provides comprehensive analysis capabilities for pre-5G signals based on the Verizon 5G open trial specifications.  With the standardized pre-5G technical specifications, engineers are already taking steps toward signal analysis.

 

vsaFigure 1. 89600 VSA users can observe pre-5G uplink and downlink physics layer measurements based on the Verizon 5G specifications. This example shows a downlink signal with 8 component carriers.

 

5G networks promise faster speeds, higher data rate, easier connectivity, and better network performance. Pre-5G allows users to experience certain 5G network elements while ensuring compatibility with their current 4G and LTE platforms.

 

Keysight’s latest 89600 VSA software helps break through the complexity of pre-5G, and will do the same for 3GPP 5G New Radio (NR). 3GPP 5G NR is the emerging global 5G standard. It is expected to be included in Release 15 of the 3GPP standard, which is due out later this year. With Keysight’s new 89600 VSA software release, early adopters can design and verify performance to the draft specification now, before it is published. Its extensive set of tools for demodulation and vector signal analysis enable you to explore virtually every facet of a signal and optimize even the most advanced designs.  

 

Figure 2. The 89600 VSA software will unify and accelerate the development process by providing
frequency-, time-, and modulation-domain analysis results in a single measurement.

 

The 89600 VSA software will unify and accelerate the development process by providing frequency-, time-, and modulation-domain analysis results in a single measurement. Users can observe pre-5G uplink and downlink physical layer measurements based on the Verizon 5G specifications. The 89600 VSA software is a vital and effective tool that will help blaze the trail to the 5G frontier.

 

 

The latest 89600 VSA software has over 100 recorded demo signals available for trial users. Discover the fundamentals of pre-5G air interface parameters, physical channels and signals.

 

Read the technical overview for more information on pre-5G signal analysis.

 

See the vast capabilities of the 89600 VSA Pre-5G Modulation Analysis in this four-minute video tour.

 

 

You can now jump start your 5G development for Verizon 5G, and continue for upcoming 3GPP 5G NR with a free trial of the 89600 VSA software.

 

“The important thing in science is not so much to obtain new facts as to discover new ways of thinking about them.”-Sir William Henry Bragg Inventor of X-ray spectrometer, Nobel Prize for Physics, 1915

Introduction

Much like Sir William Henry Bragg stated, often, the recipe for new discovery entails new light, so elements can be viewed in a fresh perspective.

 

This week on Tim’s Blackboard, I will start with the motivation for Fourier to introduce his series, follow by his unintentionally visit to the frequency domain, and end with how the new frequency domain view helps us understand the root cause of eye closure. 

 

Fourier and “The Analytic Theory of Heat”

Whenever frequency domain is in a conversation, there is no escape from mentioning the name of this famous mathematician and physicist: Joseph Fourier.

 

Fig. 1: Jean-Baptiste Joseph Fourier. Image credit: https://commons.wikimedia.org

 

Although well-known for Fourier Series and Transform, in his 1800’s publications, the French-born scientist in Fig. 1 was originally analyzing heat flow.  

 

To solve the heat equation in a metal plate, Fourier had the idea to decompose a complicated heat source as a linear combination of simple sine and cosine waves, and to write the solution as a superposition of the corresponding eigen-solutions. Nowadays, this superposition or linear combination is known as the Fourier Series [1].

 

Fourier Series: Unfamiliar Yet Familiar

Although trying to represent a complicated function with linear combinations of sine and cosines might sound foreign, the decomposition of a complicated element into simpler sub-elements is a familiar idea.

 

In his lecture on Fourier Series, MIT Professor Dennis Freeman cleverly illustrates the similarity between Fourier Series and the Cartesian representation of an arbitrary vector in 3D-space [2].

 

Fig. 2: An arbitrary vector in 3D-space.

 

Shown in Fig. 2 is an arbitrary vector in 3D-space. Without additional coordinate information, our view of the vector is a geometric one: a line. However, as soon as we place the vector in a coordinate system, the vector geometry translates to vector magnitudes and directions. In a Cartesian system, there are three different components: one in x-direction, one in y-direction and one in the z-direction, as demonstrated in Fig. 3.

 

Fig. 3: Representation of an arbitrary vector in 3D-space in Cartesian coordinates. The original vector is separated into three components of various magnitudes in different directions.

 

The concept of Fourier Series is extremely similar. In Fourier Series, one deconstructs a periodic function into sines and cosines of different frequencies. The different frequencies of cosines and sines are analogous to the different directions in the Cartesian coordinates.

 

Take a classic ideal square wave for example. Fig. 4 shows the comparison between representing a vector in 3D-space and expressing a square wave with Fourier Series.

 

Fig. 4: Comparison between a vector in 3D-space and an ideal square wave expressed in Fourier Series. The sine waves of different frequencies correspond to the different directions in Cartesian coordinate system. 

 

It is important to note in Fig. 4, the “…” in the Fourier Series expression indicates an infinite sum of sines with only odd harmonics. Mathematically, we write

 

 

Unlike the vector in 3D-space, where only three magnitudes and directions are needed to recreate the vector, we need infinite number of magnitude and directions to truthfully represent the ideal square wave in Fourier Series.

 

But Tim, what if instead of infinite number of odd harmonics, I only have the first 10?

 

In ADS, there is a Vf_Square source that lets you experiment with the number of harmonics you desire to be in the Fourier Series. The result of the simulation is in Fig. 5.

 

Fig. 5: ADS simulation result of including only the first 10 odd harmonics in the square wave.

 

Stepping into Frequency Domain

Writing a function in the form of Fourier Series gives us a fresh perspective. Specifically, by looking at the Fourier Series construction of a function, we are able to visualize the frequency components present in the function and the strength of each frequency component.

 

Let’s revisit the ideal square wave expression, the Fourier Series shown below has both “direction” and “magnitude.”

 

 

Because the multiplication factor in front of ω0 indicates the frequency of the sine wave, we plot the factor, n, on the x-axis. For each nth harmonic, there is a specific magnitude that goes on the y-axis. Fig. 6 illustrates the parameters we are plotting.

Fig. 6: Illustration of what goes on a frequency domain plot. On the x-axis, we plot the harmonics, and we plot the magnitude on the y-axis.

 

Fig. 7 displays the log-log plot of frequency domain spectrum up to the 100th harmonic of the sine wave component that makes up the ideal square wave. The 1/n relationship of the magnitude and harmonic is made clear in a log-log plot.  

 

Fig. 7: Frequency spectrum of an ideal square wave up to the 100th harmonic. The magnitude of the harmonics is inversely proportional to the order of each harmonic. 

 

Extension of Fourier Series

Indeed, Fourier Series is very useful when it comes to representing a periodic waveform. Nonetheless, one major limitation of Fourier Series is the assumption of periodic waveform.

 

Let’s take the impulse response of a channel for example. Fig. 8 is the waveform of a channel we investigated in Dirac Delta Misnomer. The impulse response is NOT a periodic function. If I am interested in the impact of the channel on different frequency components, I would need a way to transform the aperiodic time domain response to the frequency domain.

Fig. 8: Time domain impulse response of a channel is not a periodic function.

 

In the next post, I will show that with the help of Fourier transform, an extension of Fourier Series, I can convert the time domain impulse response to the frequency domain insertion loss, as shown in Fig. 9.

 

Fig. 9: Frequency domain representation of the time domain impulse, also known as the insertion loss.

 

Because the insertion loss plot gives us valuable information on how each frequency component is affected by the channel, we can then identify the root cause of eye closure.

 

Conclusion

As Sir William Bragg points out, new discovery requires a new point of view. There is no doubt Fourier’s approach to the heat equation is a novel one.

 

By using Fourier Series, we examine the ideal square wave through the frequency domain looking glass. In the next weeks, we will see how we apply Fourier transform to understand the root cause of eye closure.    

 

That's this week's Tim's Blackboard. See you in two weeks!

 

Experiment with the square wave source: 

References

[1]

Wikipedia contributors, "Fourier series," 9 August 2017. [Online]. Available: https://en.wikipedia.org/w/index.php?title=Fourier_series&oldid=786176863.

[2]

D. Freeman, "6.003 Signals and Systems," Massachusetts Institute of Technology: MIT OpenCourseWare, Fall 2011. [Online]. Available: https://ocw.mit.edu.

 

Demands for faster data speeds and more reliable services are at an all-time high. 5G is predicted to meet these demands, and much more. Although 5G is currently still in the planning stages, researchers are uncovering solutions that were previously thought impossible. Until recently, mm-waves have been viewed as unsuitable for mobile communication. However, new research has shown that propagation issues can be overcome, with help from mm-wave small-circuit designs.

 

Plextek RFI is a leading company in 5G design, specializing in the design and development of RFICs, MMICs and microwave/mm-wave modules. The designers at Plextek RFI manage their own RF On Wafer (RFOW) test facility, providing several leading foundries highly developed design services. Their designs are used in a wide range of applications from test instrumentation to infrastructure equipment and the latest mm-wave 5G systems.

 

Plextek RFI also has a growing archive of video tutorials on various design topics in a wide range of applications from test instrumentation to infrastructure equipment and the latest mm-wave 5G systems.

The most recent video tutorial provides a visual demonstration of the design, layout, and performance of a Dual-Band 5G Power Amp using Keysight ADS.

 

dual band layout

Figure 1. Full layout of a mm-wave 5G dual-band power amplifier.

 

Dual-band power amps are vastly popular in proposed 5G designs due to the wide range of frequencies used in 5G applications. They perform almost as well as two single-band PAs combined, as they are capable of electronically switching their operating band between the 26GHz and 32GHz 5G bands. They are small, inexpensive, and with ADS, easy to design.

 

ADS schematic of dual-band PA

Figure 2: ADS schematic of three-stage dual-band power amplifier.

 

s-parameters pf PHEMT switch transistor

Figure 3: S-parameters vs. frequency of a pHEMT switch transistor, used to alter effects of transmission lines in low and high bands.

 

 

Watch the 20-minute tutorial video to dive further into each stage of the power amp design, and to see the effects of the pHEMT switch by simulating the S-parameters at high and low band.

 

For more information on Plextek RFI, go to here.

 

See more tutorials by Plextek RFI here.

 

 

If you are interested in learning more about 5G design using ADS, an upcoming webcast will cover the “Circuit Design Phase” of a 5G system done all in ADS.

Click here to watch the webcast.

 

apply for free trial

Apply for a free trial of ADS.

This Case Study highlights work published in a recent paper in IEEE Power Electronics Magazine entitled Utilizing Modern Design Methodologies for Wide-Bandgap Power Electronics by my colleague here at Keysight EEsof EDA, Chris Mueth, and by Rakesh K. Lal of Transphorm, Inc. The high di/dt and dV/dt edges in switched-mode power supplies (SMPSs) combined with layout parasitics can create unwanted voltage spikes. The authors demonstrate that EM-circuit co-simulation can predict these effects. With the insights from this predictive tool in hand, they rapidly explore the design space and mitigate the impairment. The time and money spent on board spins is reduced and the time to market improved.

The Challenge

Since GaN switches are intrinsically very fast, one can have a very high change in voltage versus a given change in time (dv/dt) (>300 V/ns) and a change in current versus a given change in time (di/dt) (>5 A/ns). So, designers need to use good design practice for high-frequency layouts. Three cardinal rules that apply are:

  • Minimize capacitances to ground or other nodes at high dv/dt nodes to minimize Ispike = C dV/dt
  • Minimize parasitic inductance in high di/dt branches to minimize Vspike = L di/dt
  • Guard or shield high-impedance signal nodes, such as the gate of a drive transistor with appropriate guard rings and shields.

Physical prototypes are costly and time consuming to build and don't give insight into details like current crowding (which is indicative of excess inductance). But virtual prototyping in a tool like ADS (which allows EM circuit co-simulation) do exactly this. 

 

The Solution

The authors used ADS to gain insight into design weaknesses. The key point here is that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along with the effects of the layout. You can plot the voltage spikes and do "what if..." design space exploration, such as using a ground plane for the return current, to minimize their effects.

 

The Results

 

The Transphorm reference design analysis used the Momentum method of moments EM field solver. The EM-model extraction took roughly one hour. The tool automatically creates the components representing the layout from the port-to-port network parameters generated by the EM field solver. The analysis tool then simulated the circuit schematic including the extracted model in the time domain.

 

After experimenting with various "virtual prototypes", the final reference design utilized two power planes, which were poured onto two different PCB layers. This provided the best possible reduction in power plane inductive parasitics. In addition, the power planes were placed close together and provided an additional capacitance benefit. As a best practice, the ground layer was located under the main trace routing layer to provide additional capacitance to help reduce the stray inductance of these traces. 

 

The reference design produced an efficiency of 98.5% for the buck half-bridge configuration. This correlates well with the 98.3% efficiency seen in the simulation. The gate-driver waveforms also correlated well.

 

Are you working on switched-mode power converters? Do you face the same challenge? Or something else? Please log in and leave a comment and/or "like" this posting!

 

Best regards,

-- Colin

 

PS Here's the link to request an ADS evaluation license if you want to try it.

The trend in switched-mode power supplies is to use wide band gap devices because these enable a higher switching frequency and higher edge speeds (the “di/dt” of the switched loop). These two in turn enable a smaller, lighter, cheaper power supply because the energy storage capacitors and magnetics can be smaller if you top them off more frequently. The higher edge speeds enable higher efficiency because there’s less heat dissipated when you have lower switching losses because the transistors spend less time in the dissipative cross over region.

 

These high slew rates come with a dark side, in particular the large spike voltage and noise generated by the layout parasitics, particularly inductance, of the PCB layout traces. This phenomenon is often called conductive electromagnetic interference (conducted EMI).

 

My colleague, Andy Howard, talked about how to deal with this a while back in his video entitled “How to Design DC-to-DC Power Converters”, but a frequently asked question was “When should I start to worry about layout parasitics inductance? Is there a quick rule of thumb that says kind of ‘Caution: Further investigation’s needed?’” The answer is "Yes!" and this follow up video is about how to make these estimates. Here's the link:

 

How to Estimate Voltage Spikes from Layout Parasitic Inductance in Switched-Mode Power Supplies

 

Layout parasitics cause spike voltages in the switched loop of a switched-mode power supply

Welcome to Tim’s Blackboard! This is the place to find discussions on interesting topics related to signal integrity and power integrity.

 

This week we are taking a break from Signal Integrity. In this post, I will “demystify ultra-low impedance measurement.”

 

Introduction

To measure ultra-low DC resistance, instead of using a traditional 2-terminal sensing, one uses 4-terminal Kelvin sensing to avoid contact resistance. Similarly, instead of using the 1-port method to measure low impedance of the Power Distribution Network (PDN), we use the 2-port shunt technique, shown in Fig. 1.

 

Fig. 1: 2-port technique for ultra-low impedance measurement.

 

In the following paragraphs, I will show you that not only does the 2-port technique give us more measurable signal levels, it also helps us reduce the effect of contact resistance. 

 

Why Use the 2-port Technique?

In the March 2010 issue of the PCB Design Magazine, Mr. Istvan Novak pointed out “S11 VNA Measurements Don’t Work for PDN Measurements.

 

It is true. If I assume the device under test, the PDN, has 10 mOhm impedance and port impedance is 50 Ohm, the S11 calculation,

 

 

 

gives me -0.003 dB, which is easily masked by noise or bad calibration.  

 

Even if I have an ideal VNA with no noise and with perfect calibration, the contact resistance from the test fixture to the device under test, typically in mOhm range, is large enough to influence the result of the measurement significantly.

 

Fig. 2: Illustration of contact resistance in series with impedance under test.

 

To tell how contact resistance impacts the impedance calculation, I need to derive the extracted impedance in terms of measured S11. Using the schematic shown in Fig. 2, I would write

 

 

According to the impedance extraction equation, the contact resistance is directly influencing the extracted impedance. Worse yet, since the impedance and the contact resistance are of the same order of magnitude, I know the impedance extraction result is highly sensitive to the contact resistance.     

 

2-port Ultra-low Impedance Measurement Technique  

Shown in Fig. 3, the 2-port ultra-low impedance technique connects the device under test in shunt with the ports and uses S21 to extract the impedance under test.

Fig. 3: Ultra-low impedance measurement uses S21 to measure and extract the impedance under test.

 

Note that because S21 is the response of port 2 by the excitation from port 1, it’s analogous to using port 1 as a current source and port 2 as a voltage probe in DC 4-terminal sensing.     

 

Applying S-parameter analysis to the circuit in Fig. 3, the S21 of the device under test is: 

 

 

Putting in the numbers (Zport = 50 Ohm, ZDUT = 10 mOhm),

 

 

Given a good VNA, I should be able to measure down to -68 dB.

 

As shown, the 2-port technique is more suitable for ultra-low impedance measurement. The measured S21 is in the -60 to -80 dB range, more approachable than the S11 in milli-dB range.

 

So far, I have shown S21 produces more measurable signal levels than the S11 measurement. Next, I will demonstrate another great feature of 2-port measurement: insensitivity to contact resistance.   

 

2-port Technique Reduces Impact of Contact Resistance

Using the previous result, I continue and solve for the ideal extracted impedance given measured S21,

 

 

As shown, if there were no contact resistance, above calculation with measured S21 gives exactly the impedance under test. Let’s see what happens when I put the contact resistance back in the setup.

 

Fig. 4: Illustration of 2-port low impedance measurement setup with contact resistance.

 

Found in Fig. 4 is the 2-port measurement setup with contact resistance included. With the contact resistance, the extracted impedance is no longer just the device under test. The result of the impedance extraction is

 

where

 

 

Now, knowing both the contact resistance and the impedance of the device under test are in the mOhm range, I know the resistance error constant, Kr, is dominated by the sum of the contact resistance:

 

In addition, if I am measuring a low impedance PDN, S21 is going to be a number much smaller than 1, that is,

 

 

Given the approximations, I can rewrite the 2-port extracted impedance,

 

 

 

Great news! Since both S21 and the contact resistance are small numbers, the product is going to be even smaller! Consequently, as long as I am measuring low impedance, where S21 is a small value, the 2-port measurement technique is NOT sensitive to the contact resistance.  

 

Ultra-low Impedance Measurement Demystified  

Having derived the impedance extraction equations for both 1-port and 2-port measurements, I have demonstrated that the 2-port technique is a wonderful method to measure ultra-low impedance.

 

The 2-port low-impedance technique can examine more than just PDN. Because of the ability to measure ultra-low impedance, the technique is also useful to investigate the skin-depth of copper traces and a capacitor’s equivalent series resistance and equivalent inductance.    

 

That's this week's Tim's Blackboard. See you in two weeks!

 

To download ADS to create a virtual ultra-low impedance 2-port measurement test bench:

Further Reading

Ultra-Low Impedance Measurements Using 2-Port Measurements