Skip navigationLog in to follow, share, and participate in this community. The Tower of Babel (Genesis 11:1-9) is a story to explain why the world's peoples speak different languages: https://en.wikipedia.org/wiki/Tower_of_Babel The explanation of why the world's circuit simulators speak different languages is more mundane... There were many attempts at circuit simulation programs before, but one called… (Show moreShow less) Want to find out how to design a smaller, lighter, and lower cost switched-mode power supply? Please register for our Keysight Engineering Education (KEE) Webinar on this topic, that we will present on Wednesday January 30th 2019, 10AM Pacific/1PM Eastern. Bring your questions to our live Q&A session! Registration link:… (Show moreShow less) When you create a Verilog-A version of a VHDL analog model, you'll want to verify that the two match. A convenient way to do this is to compare things like I-V curves, for example. The ADS simulator can place data for the I-V curve of your Verilog-A model directly into the dataset used by ADS Data Display. But how do you get the VHDL version in?… (Show moreShow less) In Part 1 we only translated a simple resistor. Let's look at a more complicated model, a diode with a junction capacitance that varies with voltage. Here is the model in VHDL-A, keywords in bold: library IEEE, Disciplines; use Disciplines.electrical_system.all; use IEEE.math_real.all; entity diode_cap is generic ( i0: REAL := 0.0; --… (Show moreShow less) IC-CAP comes with a powerful library of transforms and examples to help with model parameter extraction but when implementing custom analysis routines, it is sometimes necessary to use Python with external Python libraries like Numpy or SciPy for manipulating your measured data. Numpy, in particular, has a rich set of numerical processing… (Show moreShow less) In my previous post, I showed you the "all-in-one" method for adding your Verilog-A models to ADS. In this post, I'll show you another method called "shared library." It's a bit more work to set up, but it saves time in the long run because it avoids duplication of effort in each new project. If you give a project workspace to a colleague you have… (Show moreShow less) In my previous post, showed you how to create the Verilog-A code for a component model. In this post I'll show you how to import the code into ADS. If you don't have access to ADS or you're not familiar with it, I suggest you read our Quick Start Guide first. There are two strategies for adding a model to an ADS workspace, let's call them… (Show moreShow less) Verilog-AMS and VHDL-AMS are hardware description languages, capable of describing mixed-signal (i.e. analog and digital) hardware. In this series of postings, we’ll be talking about Verilog-A (i.e. the officially defined subset of Verilog-AMS that supports analog) and “VHDL-A” (not officially defined, but defined here as "the parts of VHDL-AMS… (Show moreShow less) IC-CAP comes with a powerful API for accessing internal variables and data structures. In what follows, we will illustrate an example of accessing a Setup's Inputs and Outputs to obtain parameter values for the bias conditions for our custom Python measurement routines using the TableVar object. What might be a typical approach? When… (Show moreShow less)