• 16534A CLIP

    Looking for the CLIP for this and other 16500, 16700 plugins.   Is there any chance these might surface?   Thanks Dave
    perdrix
    last modified by perdrix
  • LPA v06.20 + U4164A/M9505A bug ?

    Hi, I sometimes can not save .ala file captured by U4164A/M9505A to external PC, connected by Y1202A cable with M9048A PCIe desktop adapter; PC is running LPA v06.20.0002 software (Win7 x64 StdEmb, SSD 256Gb, 8Gb R...
    Alx
    last modified by Alx
  • Control the Logic State Analyzer using LabVIEW

    Dear sir, We are feeding input data to LSA through PODs and monitoring the output using Extractor tool. The required output data is displaying on the waveform window. The displayed output data is in Hexadecimal...
    Nagaraju
    last modified by Nagaraju
  • U4421A D-PHY analyzer and flying lead probes

    Hello,   I am using U4421 D-PHY logic and Protocol  analyzer with E5381B flying lead probe (+ socket adopter accessory). I am probing traffic between a DSI host and a DSI display. I am following "Keysight...
    ibra
    last modified by ibra
  • Does U4301A support ASPM L1 substates (L1.1 & L1.2) tracing ?

    Hi, Does U4301A PCIe 8 GT/s Analyzer support ASPM L1 sub-states  L1.1 and L1.2 tracing  (LTSSM flow)?  
    sagar
    last modified by sagar
  • Flip Flops in Xilinx FPGA dynamic probe timing core

    In my Xilinx FPGA dynamic probe I see flip flops in my timing core is this ok? Where do they come from?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • ATC2 core insertion question

    I am using a Xilinx FPGA spartan 3 and I am trying to put an Agilent Trace Core 2 (ATC2) into my design, how do I get an ATC2 into my design?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Core Inserter VS core generator in Xilinx FPGA dynamic probe

    I have a Xilinx Virtex II pro, are there advantages to using Core Inserter versus Core Generator or EDK?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • producing .cdc file with core generator or Xilinx EDK

    Core Generator or EDK does not produce the .cdc file required for automated signal name entry in the logic analyzer. If I use Core Generator or EDK instead of Core Inserter is there a way for me to manually make my ow...
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • ATC2 core size and resources

    I want to build and insert and Agilent Trace Core 2 (ATC2) into my design, but I am not sure about the its size and how many of my device resources does it take?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Dynamic probe and regular muxes comparison question

    I already put my own MUXes in my Xilinx FPGA design to better utilize debug pins instead of using FPGA dynamic probe. How is this solution better?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Differences between state and timing ATC2 cores

    I am trying to implement a dynamic probe for my xilinx Virtex II, When would I want to use an ATC2 state core (synchronous) versus a timing (asynchronous) core?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Affects of ATC2 on timing and signal routing

    I am using a Spartan 3E Xilinx FPGA, what effect does the ATC2 core have on my design’s timing? Does loading the ATC2 affect my signal routing?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • FPGA performance with ATC2 inserted

    I am worried if I implement and ATC2 core into my design, my Xilinx FPGA performance will go down, is this true?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • 2X pin Compression technology

    I heard that Agilent Trace core 2 can sample twice the number of pins, How does the 2X pin compression technology work?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • FPGA Dynamic Probe with Multiple Analyzers

    Can I use Xilinx FPGA dynamic probe with multiple logic analyzers?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Adding Signals to ATC2 core

    I created my ATC2 core for my Xilinx Virtex 4 FPGA and I forgot to assign some of the pins to the core, can I add those signals to the core or do I have to redo everything?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • JTAG cables for Xilinx FPGA dynamic probe

    What Xilinx JTAG cables work with FPGA dynamic probe? And Does the FPGA dynamic probe work if I have non-Xilinx devices on the scan chain?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Software for Altera FPGA dynamic probe

    I am using an Altera FPGA for my design, what Altera Software is required to use Agilent’s FPGA Dynamic Probe?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums
  • Altera FPGA debug pins question

    I already put my own MUXes in my Altera FPGA design to better utilize debug pins. is this solution better or not?  
    Souhaibe_Forums
    last modified by Souhaibe_Forums